System and method for increasing input/output speeds in a network switch

• US 9,130,851 B2
• Filed: 11/08/2013
• Issued: 09/08/2015
• Est. Priority Date: 06/21/2011
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ghiasi, Ali, Pillai, Velu, Chidambara, Sundar
• Primary Examiner(s): Moore, Ian N
• Assistant Examiner(s): La, Phong
• Application Number:
  US14/075,113
• Publication Number:
  US 20140064088A1
• Time in Patent Office: 669 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/60 Software-defined switches
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Claims

1. A 100 Gigabit Ethernet physical layer device, comprising:

a 100 Gigabit interface configured to receive four 25 Gigabit data flows;

a gearbox having a two to five ratio that enables a production of two 10 Gigabit data flows and two 40 Gigabit data flows for every four 25 Gigabit data flows received, the gearbox being configured to remove data flow markers inserted in data flows contained within the four 25 Gigabit data flows, the data flow markers inserted as control frames into the data flows periodically at every X 66-bit blocks, the control frames distinguishable from data frames based on a different synchronization header in the control frames as compared to the data frames; and

a plurality of output interfaces, the plurality of output interfaces including a first output interface for a first 10 Gigabit data flow, a second output interface for a second 10 Gigabit data flow, a third output interface for a first 40 Gigabit data flow, and a fourth output interface for a second 40 Gigabit data flow, the first and second 10 Gigabit data flows and the first and second 40 Gigabit data flows received by the 100 Gigabit Ethernet physical layer device within the four 25 gigabit data flows.

2. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the four 25 Gigabit data flows are received from a 100 Gigabit switch device.

3. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the four 25 Gigabit data flows are received from a 100 Gigabit packet processor device.

4. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the four 25 Gigabit data flows are received from a 100 Gigabit ASIC device.

5. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the data flow markers are based on a modification to a synchronization header.

6. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the data flow markers are based on a modification of a payload of a control frame to include an unused signal order set.

7. The 100 Gigabit Ethernet physical layer device of claim 1, wherein the data flow markers replace idle frames.

8. A 100 Gigabit Ethernet physical layer device, comprising:

a 100 gigabit interface configured for transmitting four 25 Gigabit data flows;

a physical coding sublayer module configured to receive a plurality of input data flows generated by a plurality of interface modules, the plurality of interface modules including a first 10 Gigabit interface module, a second 10 Gigabit interface module, a first 40 Gigabit interface module, and a second 40 Gigabit interface module, the physical coding sublayer module configured to insert data flow markers into each of the plurality of input data flows to produce a corresponding plurality of marked input data flows, the data flow markers inserted as control frames into the plurality of input data flows periodically at every X 66-bit blocks, the control frames distinguishable from data frames based on a different synchronization header in the control frames as compared to the data frames; and

a gearbox having a five to two ratio that enables a production of four 25 Gigabit data flows based on the plurality of marked input data flows produced by the physical coding sublayer module, wherein the four 25 Gigabit data flows produced by the gearbox are output to the 100 Gigabit interface.

9. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the four 25 Gigabit data flows are output to a 100 Gigabit switch device.

10. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the four 25 Gigabit data flows are output to a 100 Gigabit packet processor device.

11. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the four 25 Gigabit data flows are output to a 100 Gigabit ASIC device.

12. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the data flow markers are based on a modification to a synchronization header.

13. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the data flow markers are based on a modification of a payload of a control frame to include an unused signal order set.

14. The 100 Gigabit Ethernet physical layer device of claim 8, wherein the data flow markers replace idle frames.

15. A method performed by a 100 Gigabit Ethernet physical layer device, the 100 Gigabit Ethernet physical layer device having a gearbox with a five to two ratio, comprising:

receiving, by a physical coding sublayer module in the 100 Gigabit Ethernet physical layer device, a plurality of input data flows generated by a plurality of interface modules, the plurality of interface modules including a first 10 Gigabit interface module, a second 10 Gigabit interface module, a first 40 Gigabit interface module, and a second 40 Gigabit interface module;

inserting, by the physical coding sublayer module, data flow markers into the plurality of input data flows to produce a corresponding plurality of marked input data flows, the data flow markers inserted as control frames into the plurality of input data flows periodically at every X 66-bit blocks, the control frames distinguishable from data frames based on a different synchronization header in the control frames as compared to the data frames;

producing, by the gearbox having a five to two ratio, four 25 Gigabit data flows based on the plurality of marked input data flows; and

transmitting the four 25 Gigabit data flows produced by the gearbox as an output on a 100 Gigabit interface of the 100 Gigabit Ethernet physical layer device.

16. The method of claim 15, wherein the data flow markers are based on a modification to a synchronization header.

17. The method of claim 15, wherein the data flow markers are based on a modification of a payload of a control frame to include an unused signal order set.

18. The method of claim 15, wherein the data flow markers replace idle frames.