Determining a position of inspection system output in design data space

• US 9,134,254 B2
• Filed: 03/14/2013
• Issued: 09/15/2015
• Est. Priority Date: 01/07/2013
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Ramachandran, Vijayakumar
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/830,539
• Publication Number:
  US 20140195992A1
• Time in Patent Office: 915 Days
• Field of Search: 716/50, 716/51
• US Class Current: 1/1
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10

Abstract

Systems and methods for determining a position of output of an inspection system in design data space are provided. One method includes merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged. The method also includes storing information for the single feature without the design data for the features that are merged. The information includes a position of the single feature in design data space. The method further includes aligning output of an inspection system for the wafer to the information for the single feature such that positions of the output in the design data space can be determined based on the position of the single feature in the design data space.

Claims

1. A method for determining a position of output of an inspection system in a design data space, comprising:

merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged;

storing information for the single feature without the design data for the features that are merged, wherein the information comprises a position of the single feature in a design data space;

aligning output of an inspection system for the wafer to the information for the single feature;

determining a position of a first portion of the output aligned to the single feature in the design data space based on the position of the single feature in the design data space; and

determining positions in the design data space of other portions of the output based on the position of the first portion of the output in the design data space, wherein the merging step, the storing step, the aligning step, determining the position of the first portion, and determining the positions of the other portions are performed by one or more computer systems.

2. The method of claim 1, wherein the output that is aligned comprises output in each of multiple swaths of output acquired by the inspection system for the wafer, and wherein determining the position of the first portion comprises determining positions of each of first portions of the output in each of the multiple swaths aligned to the single feature in the design data space based on the position of the single feature in the design data space.

3. The method of claim 1, wherein the single feature comprises a bounding polygon defining the periphery of the single feature, wherein the single feature comprises no additional features within the periphery, and wherein the bounding polygon contains no additional polygons.

4. The method of claim 1, wherein said merging eliminates any intellectual property in the design data from the information for the single feature.

5. The method of claim 1, wherein storing the information comprises storing the information in a storage medium in which the design data is not stored.

6. The method of claim 1, wherein the features that are merged have at least one lateral dimension on the wafer that is less than 100 nm, and wherein the inspection system is not capable of resolving features printed on the wafer having a lateral dimension that is less than 200 nm.

7. The method of claim 1, further comprising identifying isolated features in the design data, wherein the information that is stored does not include the design data for the isolated features.

8. The method of claim 1, wherein the features that are merged comprise dense features in the design data.

9. The method of claim 1, wherein the features that are merged comprise features in a random logic area of the design data.

10. The method of claim 1, wherein said merging comprises merging two or more sets of more than one feature in the design data into corresponding single features, wherein said storing comprises storing information for the corresponding single features without the design data for the features that are merged, and wherein the method further comprises selecting the single feature whose information will be used in the aligning step by acquiring output of the inspection system at locations of the corresponding single features on the wafer and selecting one of the corresponding single features that will provide more accurate alignment than others of the corresponding single features.

11. The method of claim 1, further comprising simulating output that will be produced for the single feature by the inspection system based on the information for the single feature, wherein said storing comprises storing the simulated output with the information for the single feature.

12. The method of claim 11, wherein said aligning comprises aligning the output of the inspection system for the wafer to the simulated output for the single feature.

13. The method of claim 1, wherein said merging comprises merging two or more sets of more than one feature in the design data into corresponding single features, and wherein the method further comprises selecting the single feature whose information will he used in the aligning step from the corresponding single features.

14. The method of claim 1, wherein the design data is not used by the inspection system during inspection of the wafer.

15. The method of claim 1, wherein the inspection system is configured as a bright field inspection system.

16. The method of claim 1, wherein the merging step and the storing step are performed with a first of the one or more computer systems, and wherein the aligning step, determining the position of the first portion, and determining the positions of the other portions are performed with a second of the one or more computer systems.

17. A method for determining a position of output of an inspection system in a design data space, comprising:

aligning output of an inspection system for a wafer to information for a single feature, wherein more than one feature in design data for the wafer were merged into the single feature that has a periphery that encompasses all of the features that were merged, and wherein the information comprises a position of the single feature in a design data space;

determining a position of a first portion of the output aligned to the single feature in the design data space based on the position of the single feature in the design data space; and

determining positions in the design data space of other portions of the output based on the position of the first portion of the output in the design data space, wherein aligning the output, determining the position of the first portion, and determining the positions of the other portions are performed using a computer system.

18. The method of claim 17, wherein the computer system is part of an inspection system, and wherein the features were merged by a computer system of an electronic design automation tool.

19. A system configured to determine a position of output of an inspection system in a design data space, comprising:

a computer subsystem configured for;

merging more than one feature in design data for a wafer into a single feature that has a periphery that encompasses all of the features that are merged; and

storing information for the single feature without the design data for the features that are merged, wherein the information comprises a position of the single feature in a design data space; and

an inspection subsystem configured for;

scanning the wafer to generate an output for the wafer;

aligning the output for the wafer to the information for the single feature;

determining a position of a first portion of the output aligned to the single feature in the design data space based on the position of the single feature in the design data space; and

determining positions in the design data space of other portions of the output based on the position of the first portion of the output in the design data space.

20. The system of claim 19, wherein the computer subsystem is part of an electronic design automation tool, and wherein the inspection subsystem is not part of the electronic design automation tool.

21. The system of claim 19, wherein the output that is aligned comprises output in each of multiple swaths of output acquired by the inspection subsystem for the wafer, and wherein determining the position of the first portion comprises determining positions of each of first portions of the output in each of the multiple swaths aligned to the single feature in the design data space based on the position of the single feature in the design data space.

22. The system of claim 19, wherein the single feature comprises a bounding polygon defining the periphery of the single feature, wherein the single feature comprises no additional features within the periphery, and wherein the bounding polygon contains no additional polygons.

23. The system of claim 19, wherein said merging eliminates any intellectual property in the design data from the information for the single feature.

24. The system of claim 19, wherein storing the information comprises storing the information in a storage medium in which the design data is not stored.

25. The system of claim 19, wherein the features that are merged have at least one lateral dimension on the wafer that is less than 100 nm, and wherein the inspection subsystem is not capable of resolving features printed on the wafer having a lateral dimension that is less than 200 nm.

26. The system of claim 19, wherein the computer subsystem is further configured for identifying isolated features in the design data, and wherein the information that is stored does not include the design data for the isolated features.

27. The system of claim 19, wherein the features that are merged comprise dense features in the design data.

28. The system of claim 19, wherein the features that are merged comprise features in a random logic area of the design data.

29. The system of claim 19, wherein said merging comprises merging two or more sets of more than one feature in the design data into corresponding single features, wherein said storing comprises storing information for the corresponding single features without the design data for the features that are merged, and wherein the computer subsystem is further configured for selecting the single feature whose information will be used in the aligning step by acquiring output of the inspection subsystem at locations of the corresponding single features on the wafer and selecting one of the corresponding single features that will provide more accurate alignment than others of the corresponding single features.

30. The system of claim 19, wherein the computer subsystem is further configured for simulating output that will be produced for the single feature by the inspection subsystem based on the information for the single feature, and wherein said storing comprises storing the simulated output with the information for the single feature.

31. The system of claim 30, wherein said aligning comprises aligning the output of the inspection subsystem for the wafer to the simulated output for the single feature.

32. The system of claim 19, wherein said merging comprises merging two or more sets of more than one feature in the design data into corresponding single features, and wherein the computer subsystem is further configured for selecting the single feature whose information will be used in the aligning step from the corresponding single features.

33. The system of claim 19, wherein the design data is not used by the inspection subsystem during inspection of the wafer.

34. The system of claim 19, wherein the inspection subsystem is configured as a bright field inspection subsystem.