Contactless wafer probing with improved power supply
First Claim
1. An integrated circuit disposed on a semiconductor substrate, comprising:
- an inductive or capacitive wireless communication structure located on a die region of the integrated circuit and configured to wirelessly receive a test stimulus vector to test circuitry on the die region; and
a plurality of landing regions located on the die region and buried at different layers having different respective heights as measured from an uppermost surface of the semiconductor substrate, wherein the respective landing regions have sizes and locations suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact therewith to provide a DC power supply to the circuitry on the die region at various stages during manufacture of the integrated circuit while the test stimulus vector is wirelessly received.
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Accused Products
Abstract
Some embodiments relate to an integrated circuit. The integrated circuit includes an inductive or capacitive wireless communication structure located on a die region of the integrated circuit. This wireless communication structure is configured to wirelessly receive a test stimulus vector to test circuitry on the die region. The integrated circuit also includes a landing region having a size and location suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact with the landing region. The landing region provides a DC power supply to the circuitry on the die region while the test stimulus vector is wirelessly received.
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Citations
17 Claims
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1. An integrated circuit disposed on a semiconductor substrate, comprising:
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an inductive or capacitive wireless communication structure located on a die region of the integrated circuit and configured to wirelessly receive a test stimulus vector to test circuitry on the die region; and a plurality of landing regions located on the die region and buried at different layers having different respective heights as measured from an uppermost surface of the semiconductor substrate, wherein the respective landing regions have sizes and locations suitable to allow a conductive needle or conductive probe to come into direct physical and electrical contact therewith to provide a DC power supply to the circuitry on the die region at various stages during manufacture of the integrated circuit while the test stimulus vector is wirelessly received. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor wafer, comprising:
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a plurality of die regions, wherein respective die regions include respective integrated circuit structures corresponding thereto; scribe lines arranged on the semiconductor wafer between neighboring die regions; a power bus arranged in a scribe line on the semiconductor wafer and extending continuously between two or more of the plurality of die regions to concurrently couple a DC power supply to the two or more of the plurality of die regions; and respective inductive or capacitive communication structures arranged on respective die regions;
wherein an inductive or capacitive communication structure on a die region is configured to wirelessly receive a test stimulus vector to an integrated circuit structure on the die region. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A method of automated testing for a semiconductor wafer, comprising:
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placing a conductive power conduit in physical and electrical contact with a power bus on the wafer, wherein the power bus is arranged in a scribe line, which separates neighboring rows or neighboring columns of integrated circuit structures from one another, and wherein the power bus extends continuously between multiple integrated circuit structures on the wafer to electrically couple the multiple integrated circuit structures to one another; concurrently supplying a DC power to the multiple integrated circuit structures on the wafer via the conductive power conduit and the power bus; and while the DC power is supplied to the integrated circuit structures, wirelessly transmitting stimulus test vectors to wireless communication structures on the integrated circuit structures to test functionality of the integrated circuit structures. - View Dependent Claims (16, 17)
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Specification