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Continuous application and decompression of test patterns and selective compaction of test responses

  • US 9,134,370 B2
  • Filed: 09/09/2013
  • Issued: 09/15/2015
  • Est. Priority Date: 11/23/1999
  • Status: Expired due to Term
First Claim
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1. A circuit, comprising:

  • a parallel-in serial-out register; and

    a decompressor comprising a phase shifter and a linear feedback shift register (LFSR), the LFSR being coupled between an output of the register and an input of the phase shifter,the parallel-in serial-out register being configured to load compressed test pattern bits in parallel and apply the compressed test pattern bits serially to the LFSR of the decompressor, andthe decompressor being configured to decompress the compressed test pattern bits into decompressed test pattern bits.

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