Recovery from programming failure in non-volatile memory

• US 9,135,113 B2
• Filed: 10/08/2013
• Issued: 09/15/2015
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Ojalvo, Shai, Gurgi, Eyal, Kasorla, Yoav
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/048,492
• Publication Number:
  US 20150100847A1
• Time in Patent Office: 707 Days
• Field of Search: 714/763, 714/764, 714/773, 714/718
• US Class Current: 1/1
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, applying ECC decoding to the recovered data using the reliability metrics and reprogramming the recovered data.

Claims

1. A method, comprising:

receiving data encoded with an Error Correction Code (ECC) for storage in a plurality of memory cells;

buffering the data in a volatile buffer;

writing the buffered data to the plurality of memory cells;

overwriting a first bit of the data in the volatile buffer with information indicative of a success in writing the first bit in a given one of the plurality of memory cells;

upon detecting a failure in writing the buffered data to the memory cells, producing recovered data by reading both the volatile buffer and the plurality of memory cells;

assigning reliability metrics to a second bit of the recovered data depending on whether the second bit was read from the volatile buffer or from a particular memory cell of the plurality of memory cells;

applying ECC decoding to the recovered data using the reliability metrics; and

re-programming the recovered data.

2. The method according to claim 1, wherein producing the recovered data comprises setting the second bit of the recovered data to a corresponding bit value read from the plurality of memory cells if the corresponding bit value read from the volatile buffer is a success indication, and setting the second bit of the recovered data to the corresponding bit value read from the volatile buffer if the corresponding bit value read from the volatile buffer differs from the success indication.

3. The method according to claim 1, wherein assigning the reliability metrics comprises assigning to the second bit that was read from a particular memory cell of the plurality of memory cells lower reliability metrics relative to the reliability metrics assigned to bits that were read from the volatile buffer.

4. The method according to claim 1, wherein the data comprises a portion of storage data received from a host, and comprising discarding the data after buffering the data in a volatile buffer, irrespective of whether a remaining portion of the storage data is stored in the plurality of memory cells.

5. The method according to claim 1, wherein the plurality of memory cells are included in a memory device, wherein reading the volatile buffer and the plurality of memory cells is performed by circuitry internal to the memory device, and wherein applying the ECC decoding is performed by a memory controller that controls the memory device.

6. The method according to claim 1, wherein reading the plurality of memory cells comprises reading the bits from the plurality of memory cells using one or more dedicated read thresholds, which are dedicated for recovery from programming failures and differ from normal read thresholds used for data readout.

7. The method according to claim 1, wherein re-programming the recovered data comprises writing the recovered data to a group of the plurality of memory cells other than the memory cells in which the failure has occurred.

8. The method according to claim 1, wherein producing the recovered data comprises writing the recovered data in-place in the volatile buffer.

9. An apparatus, comprising:

a memory, which comprises multiple memory cells; and

storage circuitry configured to;

receive data encoded with an Error Correction Code (ECC) for storage in the multiple memory cells;

buffer the data in a volatile buffer;

write the buffered data to the multiple memory cells;

overwrite a first bit of the data in the volatile buffer with information indicative of a success in writing the first bit of the data in a given one of the multiple memory cells;

produce recovered data in response to detecting a failure in writing the buffered data to the multiple memory cells, by reading both the volatile buffer and the memory cells;

assign reliability metrics to a second bit of the recovered data depending on whether the second bit was read from the volatile buffer or from the multiple memory cells; and

apply ECC decoding to the recovered data using the reliability metrics; and

re-program the recovered data.

10. The apparatus according to claim 9, wherein to produce the recovered data, the storage circuitry is further configured to set the second bit of the recovered data to a corresponding bit value read from the multiple memory cells if the corresponding bit value read from the volatile buffer is a success indication, and set the second bit of the recovered data to the corresponding bit value read from the volatile buffer if the corresponding bit value read from the volatile buffer differs from the success indication.

11. The apparatus according to claim 9, wherein to assign the reliability metrics, the storage circuitry is further configured to assign to the second bit that was read from the multiple memory cells lower reliability metrics relative to reliability metrics assigned to the bits that were read from the volatile buffer.

12. The apparatus according to claim 9, wherein the data comprises a portion of storage data received from a host, and wherein the storage circuitry is further configured to discard the data after buffering the data in a volatile buffer, irrespective of whether a remaining portion of the storage data is stored in the multiple memory cells.

13. The apparatus according to claim 9, wherein the multiple memory cells are included in a memory device, and wherein the storage circuitry includes circuitry internal to the memory device configured to read the volatile buffer and the multiple memory cells, and a memory controller configured to apply the ECC decoding.

14. The apparatus according to claim 9, wherein the storage circuitry is further configured to read the bits from the multiple memory cells using one or more dedicated read thresholds, which are dedicated for recovery from programming failures and differ from normal read thresholds used for data readout.

15. The apparatus according to claim 9, wherein to re-program the recovered data, the storage circuitry is further configured to re-program the recovered data to a group of the multiple memory cells other than the multiple memory cells in which the failure has occurred.

16. The apparatus according to claim 9, wherein the storage circuitry is further configured to produce the recovered data in-place in the volatile buffer.

17. An apparatus, comprising:

an interface, which is configured to communicate with a memory comprising multiple memory cells; and

storage circuitry configured to;

receive data encoded with an Error Correction Code (ECC) for storage in the multiple memory cells;

buffer the data in a volatile buffer;

write the buffered data to the multiple memory cells;

overwrite a first bit of the data in the volatile buffer with information indicative of a success in writing the first bit of the data in a given one of the multiple memory cells;

produce recovered data in response to detecting a failure in writing the buffered data to the multiple memory cells, by reading both the volatile buffer and the memory cells

assign reliability metrics to a second bit of the recovered data depending on whether the second bit was read from the volatile buffer or from the multiple memory cells; and

apply ECC decoding to the recovered data using the reliability metrics; and

re-program the recovered data.

18. The apparatus according to claim 17, wherein to produce the recovered data, the storage circuitry is further configured to set the second bit of the recovered data to a corresponding bit value read from the multiple memory cells if the corresponding bit value read from the volatile buffer is a success indication, and to set the second bit of the recovered data to the corresponding bit value read from the volatile buffer if the corresponding bit value read from the volatile buffer differs from the success indication.

19. The apparatus according to claim 17, wherein to assign the reliability metrics, the storage circuitry is further configured to assign to the second bit that was read from the multiple memory cells lower reliability metrics relative to reliability metrics assigned to the bits that were read from the volatile buffer.

20. The apparatus according to claim 17, wherein the data comprises a portion of storage data received from a host, and wherein the storage circuitry is further configured to discard the data after buffering the data in a volatile buffer, irrespective of whether a remaining portion of the storage data is stored in the multiple memory cells.