Data storage assembly for archive cold storage

• US 9,135,205 B1
• Filed: 01/29/2015
• Issued: 09/15/2015
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Ryan, Robert P., Jenkins, Dean M.
• Primary Examiner(s): HUBER, PAUL W
• Application Number:
  US14/608,980
• Time in Patent Office: 229 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: G11B 5/4806 specially adapted for disk drive assemblies, e.g. assembly prior to operation, hard or flexible disk drives G11B5/488 - G11B5/54 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage assembly for cold storage. The data storage assembly includes a circuit board and a plurality of hard disk assemblies (HDA). Each HDA includes a platter and a head assembly to read and write data on the platter. The circuit board includes a processor and a read channel. The processor acts as a hard disk controller for the plurality of HDAs and controls the platters. The processor further manages which HDAs are active at a time and the read channel is shared by the plurality of HDAs.

Claims

1. A data storage assembly comprising:

a circuit board comprising;

a processor; and

a read channel; and

a plurality of hard disk assemblies (HDAs), each HDA comprising;

a platter configured to store data; and

a head assembly configured to read data from and write data to the platter;

wherein the processor is configured to be a hard disk controller (HDC) for the plurality of HDAs and manage which of the plurality of HDAs are active at a time, and the plurality of HDAs are configured to share a read channel among the plurality of HDAs.

2. The data storage assembly of claim 1, wherein the processor is further configured to determine which one of the plurality of HDAs to utilize for a data command.

3. The data storage assembly of claim 1, wherein the processor is further configured to perform error recovery for reading and writing to the plurality of HDAs.

4. The data storage assembly of claim 1, further comprising a motor controller configured to spin the platters of the plurality of HDAs and move the head assemblies of the plurality of HDAs across the respective platters of the plurality of HDAs.

5. The data storage assembly of claim 1, further comprising a multiplexer configured to communicate with each of the plurality of HDAs.

6. The data storage assembly of claim 1, further comprising a plurality of sensors configured to detect environmental information of the plurality of HDAs.

7. The data storage assembly of claim 1, wherein the processor is further configured to manage power to the plurality of HDAs.

8. The data storage assembly of claim 1, further comprising a network connection.

9. A hard disk assembly (HDA) comprising:

a platter configured to store data;

a head assembly configured to read data from and write data to the platter;

a motor controller configured to move the head assembly across the platter; and

a circuit board configured to communicate between the HDA and a read channel external to the HDA and shared among a plurality of HDAs.

10. The HDA of claim 9, wherein the circuit board is further configured to communicate between the HDA and a memory external to the HDA and shared among a plurality of HDAs.

11. The HDA of claim 9, wherein the circuit board further includes a preamp configured to reduce a Signal-to-Noise Ratio (SNR) for data read from the platter.

12. The HDA of claim 9, wherein the circuit board further includes a power large-scale integrated circuit (PLSI) configured to allow hotplugging the HDA.

13. The HDA of claim 9, wherein the circuit board further includes an emergency power off retract (EPOR) configured to safely power off the HDA.

14. The HDA of claim 9, wherein the HDA is further configured to communicate with a network via a network connection external to the HDA that is shared among the plurality of HDAs.

15. A non-transitory computer readable medium storing computer executable instructions for controlling a plurality of hard disk assemblies (HDAs), wherein when the computer executable instructions are executed by circuitry, the computer executable instructions cause the circuitry to:

manage which of the plurality of HDAs are active at a time; and

act as a hard disk controller (HDC) for the plurality of HDAs so that the plurality of HDAs share a read channel among the plurality of HDAs.

16. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to determine which one of the plurality of HDAs to utilize for a data command.

17. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to perform error recovery for reading data from and writing data to the plurality of HDAs.

18. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to act as an HDC for the plurality of HDAs so that the plurality of HDAs share a memory among the plurality of HDAs.

19. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to interface with a multiplexer to receive environmental information from a plurality of sensors for the plurality of HDAs, with each of the plurality of sensors detecting environmental information for one of the plurality of HDAs.

20. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to manage power to the plurality of HDAs.

21. The non-transitory computer readable medium of claim 15, wherein the computer executable instructions further cause the circuitry to interface with a network connection.