Convolution operation circuit and object recognition apparatus

• US 9,135,553 B2
• Filed: 07/30/2014
• Issued: 09/15/2015
• Est. Priority Date: 12/04/2008
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Kato, Masami, Yamamoto, Takahisa, Ito, Yoshinori
• Primary Examiner(s): Starks, Wilbert L
• Application Number:
  US14/447,468
• Publication Number:
  US 20140337262A1
• Time in Patent Office: 412 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 18/21 Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/06 Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent
• CPC Class Codes: G06N 5/02 Knowledge representation; Symbolic representation
• CPC Class Codes: G06T 1/00 General purpose image data processing
• CPC Class Codes: G06V 40/171 Local features and components; Facial parts eye characteristics G06V40/18; Occluding parts, e.g. glasses; Geometrical relationships

Abstract

In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder.

Claims

1. A convolution operation circuit comprising:

a plurality of multipliers each of which configured to multiply data received from a first input and a second input of respective multipliers;

a first providing unit configured to provide respective data to the first input of the plurality of multipliers;

a second providing unit configured to provide common data to the second input of the plurality of multipliers;

a plurality of cumulative adders configured to accumulate output from the plurality of multipliers;

a memory configured to store data to be provided by the first providing unit and the second providing storage unit and data output from the plurality of cumulative adders; and

a control unit configured to control operations of the first providing unit, the second providing unit, the memory, and the plurality of cumulative adders, so that the first providing unit and the second providing unit to provide data to the first input and the second input of each of the multipliers, respectively, in synchronization with operations of the cumulative adders, and the control unit transfers, during multiplications by the multipliers, data stored in the memory to the first providing unit and the second providing unit.

2. The convolution operation circuit according to claim 1, wherein the first providing unit comprising:

a first shift register configured to output respective data to the first input of the plurality of multipliers in parallel; and

a first storage unit configured to store a plurality of data to be supplied to the first shift register.

3. The convolution operation circuit according to claim 2, wherein the control unit sets a plurality of data stored in the first storage unit to the first shift register at predetermined timing and causes the first shift register to perform shift operations in synchronization with operations of the cumulative adders.

4. The convolution operation circuit according to claim 1, wherein the second providing unit comprising:

a second shift register configured to output common data to the second input of the plurality of multipliers in parallel; and

a second storage unit configured to store a plurality of data to be supplied to the second shift register.

5. The convolution operation circuit according to claim 4, wherein the control unit sets a plurality of data stored in the second storage unit to the second shift register at predetermined timing and causes the second shift register to perform shift operations in synchronization with operations of the cumulative adders.

6. The convolution operation circuit according to claim 1, further comprises a third storage unit to store a plurality of data output from the plurality of cumulative adders.

7. The convolution operation circuit according to claim 6, wherein the third storage unit comprises a third shift register including a number of registers which is greater than or equal to a number of the plurality of multipliers.

8. The convolution operation circuit according to claim 6, further comprising a non-linear conversion unit configured to perform non-linear conversion on an output from the third storage unit.

9. The convolution operation circuit according to claim 8, wherein the control unit stores in a predetermined region in the memory during a shift operation an operation result stored in the third storage unit or a result of non-linear conversion performed by the non-linear conversion unit.

10. The convolution operation circuit according to claim 6, wherein the control unit controls a reading address and a writing address in the memory and performs data transfer from the memory to the first providing unit and the second providing unit and from the third storage unit to the memory, thereby a convolution operation is performed on data stored in the memory and a further convolution operation is performed on a result of the convolution operation.

11. An object recognition apparatus including a convolution operation circuit according to claim 1.