Memory control circuit and method of controlling data reading process of memory module

• US 9,135,980 B2
• Filed: 07/09/2014
• Issued: 09/15/2015
• Est. Priority Date: 08/13/2013
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Yu, Chun-Chi, Chang, Chih-Wei, Huang, Shen-Kuo
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US14/326,869
• Publication Number:
  US 20150049562A1
• Time in Patent Office: 433 Days
• Field of Search: 365/193, 365/233.1, 365/233.13, 365/233.17
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization

Abstract

This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.

Claims

1. A memory control circuit, for controlling a data reading process of a memory module, during which the memory module transmitting a data signal and a data strobe signal that is used to recover the data signal to the memory control circuit, the data strobe signal comprising a preamble part, and the memory control circuit comprising:

a clock generating circuit for generating a clock;

a control unit coupled to the memory module and the clock generating circuit for controlling an impedance matching circuit of the memory module and generating an enabling signal according to the clock; and

a sampling circuit coupled to the control unit for sampling the data strobe signal according to the enabling signal to generate a sampling result;

wherein, the control unit first control the impedance matching circuit to make the data strobe signal keep at a fixed level before the preamble part and then controls the sampling circuit to sample the data strobe signal according to the enabling signal, and adjusts an enabling time of the enabling signal according to the sampling result and starts the process of recovering the data signal according to the enabling signal.

2. The memory control circuit of claim 1, wherein the data strobe signal is transmitted by a differential signal pair, and the control unit controls the impedance matching circuit to generate a voltage difference between two pins of the memory module that are used to transmit the differential signal pair so that the data strobe signal keeps at the fixed level before the preamble part.

3. The memory control circuit of claim 1, wherein the control unit comprises:

a delay unit for delaying the clock;

wherein the control unit uses the delay unit to delay the clock by a predetermined time and adjusts the enabling time of the enabling signal according to the delayed clock to further control the sampling circuit to sample the data strobe signal according to the enabling signal to generate a delayed sampling result, and the control unit determines the enabling time of the enabling signal according to the predetermined time and the delayed sampling result.

4. The memory control circuit of claim 3, wherein before delaying the clock, the control unit controls the impedance matching circuit to make the data strobe signal not keep at the fixed level before the preamble part.

5. The memory control circuit of claim 3, wherein a time difference between two consecutive clock edges of the clock is T, and the predetermined time is kT/n, where n is an integer larger than 1, and k is an integer larger than or equal to 1 and smaller than n.

6. The memory control circuit of claim 3, wherein the control unit adjusts the enabling time of the enabling signal in order according to the plurality of clock edges of the clock, and the sampling circuit obtains a plurality of sampling results, and the control unit finds a target clock edge corresponding to a sampling result among the plurality of sampling results that matches a predetermined value and adjusts the enabling time of the enabling signal according to the target clock edge.

7. The memory control circuit of claim 6, wherein if the target clock edge is the m-th clock edge of the clock, the control unit adjusts the enabling time of the enabling signal to be close to the (m−

1)-th clock edge, where m is an integer larger than 1.

8. The memory control circuit of claim 7, wherein the delayed sampling result corresponds to the (m−

1)-th clock edge.

9. The memory control circuit of claim 8, wherein when the delayed sampling result is equal to the predetermined value, the control unit utilizes the time of the (m−

2)-th clock edge delayed by the predetermined time to be the enabling time of the enabling signal.

10. The memory control circuit of claim 1, wherein the memory module is the memory module of a DDR SDRAM.

11. A method of controlling a data reading process of a memory module, in the data reading process, the memory module transmitting a data signal and a data strobe signal that is used to recovery the data signal, and the data strobe signal comprising a preamble part, and the method comprising:

controlling an impedance matching circuit of the memory module to make the data strobe signal keep at a fixed level before the preamble part;

generating a clock;

generating an enabling signal according to the clock;

sampling the data strobe signal according to the enabling signal to generate a sampling result;

adjusting an enabling time of the enabling signal according to the sampling result; and

starting a process of recovering the data signal according to the enabling signal.

12. The method of claim 11, wherein the data strobe signal is transmitted by a differential signal pair, and the step of controlling the impedance matching circuit controls the impedance matching circuit to generate a voltage difference between two pins of the memory module that are used to transmit the differential signal pair so that the data strobe signal keeps at the fixed level before the preamble part.

13. The method of claim 11, further comprising:

delaying the clock by a predetermined time;

adjusting the enabling time of the enabling signal according to the delayed clock;

sampling the data strobe signal according to the enabling signal to generate a delayed sampling result; and

determining the enabling time of the enabling signal according to the predetermined time and the delayed sampling result.

14. The method of claim 13, further comprising:

controlling the impedance matching circuit to make the data strobe signal not keep at the fixed level before the preamble part.

15. The method of claim 13, wherein a time difference between two consecutive clock edges of the clock is T, and the predetermined time is kT/n, where n is an integer larger than 1, and k is an integer larger than or equal to 1 and smaller than n.

16. The method of claim 13, wherein the step of generating the enabling signal according to the clock comprises:

adjusting the enabling time of the enabling signal in order according to the plurality of clock edges of the clock;

and the step of sampling the data strobe signal according to the enabling signal obtains a plurality of sampling results, and the step of adjusting the enabling time of the enabling signal according to the sampling results comprises;

finding a target clock edge corresponding to a sampling result among the plurality of sampling results that matches a predetermined value and adjusting the enabling time of the enabling signal according to the target clock edge.

17. The method of claim 16, wherein if the target clock edge is the m-th clock edge of the clock, the step of controlling the enabling time of the enabling signal according to the target clock edge adjusts the enabling time of the enabling signal to be close to the (m−

1)-th clock edge, where m is an integer larger than 1.

18. The method of claim 17, wherein the delayed sampling result corresponds to the (m−

1)-th clock edge.

19. The method of claim 18, wherein the step of determining the enabling time of the enabling signal according to the predetermined time and the delayed sampling result comprises:

when the delayed sampling result is equal to the predetermined value, utilizing the time of the (m−

2)-th clock edge delayed by the predetermined time to be the enabling time of the enabling signal.

20. The method of claim 11, wherein the memory module is the memory module of a DDR SDRAM.