Three dimensional NAND string with discrete charge trap segments

• US 9,136,130 B1
• Filed: 08/11/2014
• Issued: 09/15/2015
• Est. Priority Date: 08/11/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Wada, Takayuki, Fujino, Shigehiro
• Primary Examiner(s): Laurenzi, Mark A
• Application Number:
  US14/456,515
• Time in Patent Office: 400 Days
• Field of Search: 257/324, 257/326, 257/319, 257/E29.3, 257/E21.422, 257/E21.68, 438/266, 438/268
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, etching the stack to form at least one opening in the stack, forming a buffer layer over a sidewall of the at least one opening, forming a charge storage material layer over the buffer layer, forming a tunnel dielectric layer over the charge storage material layer in the at least one opening, and forming a semiconductor channel material over the tunnel dielectric layer in the at least one opening. The method also includes selectively removing the second material layers without removing the first material layers and etching the buffer layer using the first material layers as a mask to form a plurality of separate discrete buffer segments and to expose portions of the charge storage material layer.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material different from the first material over a substrate;

etching the stack to form at least one opening in the stack;

forming a buffer layer over a sidewall of the at least one opening;

forming a charge storage material layer over the buffer layer;

forming a tunnel dielectric layer over the charge storage material layer in the at least one opening;

forming a semiconductor channel material over the tunnel dielectric layer in the at least one opening;

selectively removing the second material layers without removing the first material layers;

etching the buffer layer using the first material layers as a mask to form a plurality of separate discrete buffer segments and to expose portions of the charge storage material layer;

etching the exposed portions of the charge storage material layer using the first material layers as a mask to form a plurality of separate discrete charge storage segments;

depositing an insulating material between the first material layers to form alternating layers of insulating material layers and the first material layers;

selectively removing the first material layers to expose a sidewall of the discrete buffer segments;

etching the discrete buffer segments to expose a sidewall of the discrete charge storage segments;

forming a blocking dielectric over the sidewall of the discrete charge storage segments exposed between the insulating material layers; and

forming control gate electrodes over the blocking dielectric between the insulating material layers.

2. The method of claim 1, further comprising:

forming a sacrificial blocking layer over the buffer layer prior to the step of forming the charge storage material layer; and

etching the sacrificial blocking layer using the first material layers as a mask to expose portions of the charge storage material layer between the first material layers.

3. The method of claim 1, wherein the buffer layer comprises polysilicon.

4. The method of claim 1, wherein the charge storage material layer comprises a charge storage dielectric material.

5. The method of claim 1, wherein the charge storage material layer comprises a floating gate material.

6. The method of claim 1, further comprising etching the stack to form a back side trench in the stack;

wherein;

the steps of selectively removing the second material layers, selectively removing the first material layers, forming the blocking dielectric and forming the control gate electrodes occurs through the back side trench; and

the step of depositing the insulating material between the first material layers comprises depositing the insulating material between the first material layers through the back side trench and then recessing the insulating material to remove the insulating material from the back side trench while leaving the alternating layers of insulating material layers and the first material layers.

7. The method of claim 1, wherein:

the first material comprises a nitride; and

the second material comprises an oxide or polysilicon.

8. The method of claim 7, wherein:

the first material comprises silicon nitride;

the second material comprises silicon oxide or polysilicon; and

the control gate electrodes comprise tungsten.

9. The method of claim 1, wherein the step of forming the semiconductor channel layer in the at least one opening completely fills the at least one opening with a semiconductor channel material.

10. The method of claim 1, wherein the step of forming the semiconductor channel layer in the at least one opening forms a semiconductor channel material over the sidewall of the at least one opening but not in a central part of the at least one opening such that the semiconductor channel material does not completely fill the at least one opening and the method further comprises forming an insulating fill material in the central part of the at least one opening to completely fill the at least one opening.

11. The method of claim 1, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;

the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over a major surface of the silicon substrate and below the first device level;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

12. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material different from the first material over a substrate;

etching the stack to form at least one opening in the stack;

selectively removing a portion of the second material layers without removing the first material layers to form first recesses between the first material layers;

forming a charge storage material layer over a sidewall of the at least one opening and over exposed surface of the layers of first material and remaining second material in the first recesses;

forming a tunnel dielectric layer over the charge storage material layer in the at least one opening and in the first recesses;

forming a semiconductor channel material over the tunnel dielectric layer in the at least one opening and in the first recesses;

selectively removing the remaining second material layers without removing the first material layers;

etching the charge storage material layer using the first material layers as a mask to form a plurality of separate discrete charge storage segments;

depositing an insulating material between the first material layers to form alternating layers of insulating material layers and the first material layers;

selectively removing the first material layers to expose a sidewall of the discrete charge storage segments;

forming a blocking dielectric over the sidewall of the discrete charge storage segments exposed between the insulating material layers; and

forming control gate electrodes over the blocking dielectric between the insulating material layers.

13. The method of claim 12, further comprising:

forming a buffer layer over the sidewall of the at least one opening and over the exposed surface of the layers of first material and remaining second material in the first recesses prior to the step of forming the charge storage material layer;

etching the buffer layer using the first material layers as a mask to form a plurality of discrete buffer layer segments and to expose of the charge storage material layer between the first material layers; and

etching the discrete buffer segments to expose the discrete charge storage segments after selectively removing the first material layers.

14. The method of claim 12, further comprising:

forming a sacrificial blocking layer over the sidewall of the at least one opening and over the exposed surface of the layers of first material and remaining second material in the first recesses prior to the step of forming the charge storage material layer; and

etching the sacrificial blocking layer using the first material layers as a mask to expose portions of the charge storage material layer between the first material layers.

15. The method of claim 12, wherein the charge storage material layer comprises a charge storage dielectric material.

16. The method of claim 12, wherein the charge storage material layer comprises a floating gate material.

17. The method of claim 12, further comprising etching the stack to form a back side trench in the stack;

wherein;

the steps of selectively removing the second material layers, selectively removing the first material layers, forming the blocking dielectric and forming the control gate electrodes occurs through the back side trench; and

the step of depositing the insulating material between the first material layers comprises depositing the insulating material between the first material layers through the back side trench and then recessing the insulating material to remove the insulating material from the back side trench while leaving the alternating layers of insulating material layers and the first material layers.

18. The method of claim 12, wherein:

the first material comprises a nitride; and

the second material comprises an oxide or polysilicon.

19. The method of claim 18, wherein:

the first material comprises silicon nitride;

the second material comprises silicon oxide or polysilicon; and

the control gate electrodes comprise tungsten.

20. The method of claim 12, wherein the step of forming the semiconductor channel layer in the at least one opening completely fills the at least one opening with a semiconductor channel material.

21. The method of claim 12, wherein the step of forming the semiconductor channel layer in the at least one opening forms a semiconductor channel material over the sidewall of the at least one opening but not in a central part of the at least one opening such that the semiconductor channel material does not completely fill the at least one opening and the method further comprises forming an insulating fill material in the central part of the at least one opening to completely fill the at least one opening.

22. The method of claim 12, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;

the control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over a major surface of the silicon substrate and below the first device level;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.