Interconnect structure and methods of making same
First Claim
1. A method for forming a semiconductor interconnect structure, comprising:
- forming a dielectric layer on a substrate;
patterning the dielectric layer to form an opening in the dielectric layer;
filling the opening and covering the dielectric layer with a metal layer having a first etch rate;
planarizing the metal layer so that the metal layer is co-planar with the top of the dielectric layer;
annealing the metal layer to change the first etch rate to a second etch rate, the second etch rate being lower than the first etch rate;
forming a copper-containing layer over the annealed metal layer and the dielectric layer, wherein the copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer; and
etching the copper-containing layer to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch into the underlying annealed metal layer.
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Accused Products
Abstract
A method for forming a semiconductor interconnect structure comprises forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. The opening is filled and the dielectric layer is covered with a metal layer having a first etch rate. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is annealed to change the first etch rate into a second etch rate, the second etch rate being lower than the first etch rate. A copper-containing layer is formed over the annealed metal layer and the dielectric layer. The copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch thereunder.
28 Citations
20 Claims
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1. A method for forming a semiconductor interconnect structure, comprising:
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forming a dielectric layer on a substrate; patterning the dielectric layer to form an opening in the dielectric layer; filling the opening and covering the dielectric layer with a metal layer having a first etch rate; planarizing the metal layer so that the metal layer is co-planar with the top of the dielectric layer; annealing the metal layer to change the first etch rate to a second etch rate, the second etch rate being lower than the first etch rate; forming a copper-containing layer over the annealed metal layer and the dielectric layer, wherein the copper-containing layer has an etch rate greater than the second etch rate of the annealed metal layer; and etching the copper-containing layer to form interconnect features, wherein the etching stops at the top of the annealed metal layer and does not etch into the underlying annealed metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for forming an integrated circuit interconnect structure, comprising:
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forming a via opening in a dielectric layer; filling the via opening and covering the dielectric layer with a copper alloy layer having a first etch rate; planarizing the copper alloy layer so that the copper alloy layer is co-planar with the top of the dielectric layer; annealing the copper alloy layer; forming a copper-containing layer over the annealed copper alloy layer and the dielectric layer, wherein the copper-containing layer has an etch selectivity higher than the annealed copper alloy layer; and etching the copper-containing layer to form interconnect features, wherein the etching stops at the top of the annealed copper alloy layer and does not etch therein. - View Dependent Claims (13, 14, 15, 16)
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17. A method for forming a semiconductor interconnect structure, comprising:
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depositing a dielectric layer on a substrate; patterning the dielectric layer to include an opening therein; depositing within the opening a copper alloy feature having a first etch rate and extending substantially vertically into the opening in the dielectric layer, wherein no portion of the copper alloy feature is disposed outside the opening; depositing, on the dielectric layer and the copper alloy feature in the opening, a copper containing layer comprising from about 98% to about 100% copper, the copper containing layer having a second etch rate greater than the first etch rate; and patterning the copper containing layer to form a plurality of copper containing interconnect features. - View Dependent Claims (18, 19, 20)
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Specification