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Integrated chip package structure using silicon substrate and method of manufacturing the same

  • US 9,136,246 B2
  • Filed: 01/09/2004
  • Issued: 09/15/2015
  • Est. Priority Date: 12/31/2001
  • Status: Active Grant
First Claim
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1. A chip package comprising:

  • a substrate having a surface;

    a die-surrounding layer directly on said surface of said substrate;

    a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a conductive pad within said active surface of said die;

    a first dielectric layer on said active surface of said die and said first surface of said die-surrounding layer;

    a first patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said first patterned conductive layer is coupled to said conductive pad of said die through an opening in said first dielectric layer;

    a second dielectric layer on said first patterned conductive layer and on said first dielectric layer;

    a second patterned conductive layer on said second dielectric layer, wherein said second patterned conductive layer is coupled to said first patterned conductive layer through an opening in a said second dielectric layer, in which said second patterned conductive layer comprises a portion configured for external coupling of said die; and

    a comb-shaped capacitor disposed between said first patterned conductive layer and said second patterned conductive layer.

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