Integrated chip package structure using silicon substrate and method of manufacturing the same
First Claim
1. A chip package comprising:
- a substrate having a surface;
a die-surrounding layer directly on said surface of said substrate;
a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a conductive pad within said active surface of said die;
a first dielectric layer on said active surface of said die and said first surface of said die-surrounding layer;
a first patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said first patterned conductive layer is coupled to said conductive pad of said die through an opening in said first dielectric layer;
a second dielectric layer on said first patterned conductive layer and on said first dielectric layer;
a second patterned conductive layer on said second dielectric layer, wherein said second patterned conductive layer is coupled to said first patterned conductive layer through an opening in a said second dielectric layer, in which said second patterned conductive layer comprises a portion configured for external coupling of said die; and
a comb-shaped capacitor disposed between said first patterned conductive layer and said second patterned conductive layer.
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Accused Products
Abstract
An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
428 Citations
42 Claims
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1. A chip package comprising:
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a substrate having a surface; a die-surrounding layer directly on said surface of said substrate; a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a conductive pad within said active surface of said die; a first dielectric layer on said active surface of said die and said first surface of said die-surrounding layer; a first patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said first patterned conductive layer is coupled to said conductive pad of said die through an opening in said first dielectric layer; a second dielectric layer on said first patterned conductive layer and on said first dielectric layer; a second patterned conductive layer on said second dielectric layer, wherein said second patterned conductive layer is coupled to said first patterned conductive layer through an opening in a said second dielectric layer, in which said second patterned conductive layer comprises a portion configured for external coupling of said die; and a comb-shaped capacitor disposed between said first patterned conductive layer and said second patterned conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 27)
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12. A chip package comprising:
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a substrate having a surface; a die-surrounding layer directly on said surface of said substrate; a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a first conductive pad and a second conductive pad within said active surface; a first dielectric layer on said active surface of said die and on said first surface of said die-surrounding layer; and a patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said patterned conductive layer is coupled to said first conductive pad of said die through a first opening in said first dielectric layer, and wherein said patterned conductive layer is coupled to said second conductive pad of said die through a second opening in said first dielectric layer, wherein said first conductive pad is coupled to said second conductive pad through said patterned conductive layer, wherein said patterned conductive layer comprises a portion of a passive device formed in said patterned conductive layer in a single horizontal plane and a portion configured for external coupling of said die. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 42)
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29. A chip package comprising:
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a substrate having a surface; a die-surrounding layer directly on said surface of said substrate; a die having a backside surface directly on said surface of said substrate, said die disposed between a first portion of said die-surrounding layer and a second portion of said die-surrounding layer, wherein said die has an active surface substantially coplanar with a first surface of said die-surrounding layer, wherein said die comprises a first conductive pad and a second conductive pad within said active surface; a first dielectric layer on said active surface of said die and on said first surface of said die-surrounding layer; and a patterned conductive layer on said first dielectric layer, on said active surface of said die and on said first surface of said die-surrounding layer, wherein said patterned conductive layer comprises a ground piece coupled to said first conductive pad of said die through a first opening in said first dielectric layer, and coupled to said second conductive pad of said die through a second opening in said first dielectric layer, wherein said first conductive pad is coupled to said second conductive pad through said ground piece, wherein said patterned conductive layer comprises a portion of a passive device formed in said patterned conductive layer and a portion configured for external coupling of said die. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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Specification