Field effect transistor

• US 9,136,320 B2
• Filed: 04/08/2013
• Issued: 09/15/2015
• Est. Priority Date: 04/08/2013
• Status: Active Grant

• Current Assignee: Design Express Limited
• Original Assignee: Design Express Limited
• Inventors: Chang, Chun Yen
• Primary Examiner(s): Matthews, Colleen A
• Assistant Examiner(s): Mirsalahuddin, Junaiden
• Application Number:
  US13/858,439
• Publication Number:
  US 20140299923A1
• Time in Patent Office: 890 Days
• Field of Search: 257/E21.413, 257/E27.111, 257/E29.293, 257/194, 257/E21.431, 257/E29.246, 257/192, 257/288, 257/59, 257/E21.133, 257/E21.407, 257/E21.409, 257/E21.433, 257/E21.507, 257/E29.004, 257/E29.104, 257/E29.188, 257/E29.249, 257/E29.273, 257/190, 257/347, 257/55, 257/56, 257/57, 257/58, 257/60, 257/61, 257/62, 257/627, 257/628, 257/63, 257/64, 257/65, 257/67, 257/72, 257/E21.063, 257/E21.066, 257/E21.09, 257/E21.112, 257/E21.113, 257/E21.121, 257/E21.124, 257/E21.125, 257/E21.126, 257/E21.134, 257/E21.158, 257/E21.192, 257/E21.197, 257/E21.22, 257/E21.223, 257/E21.345, 257/E21.346, 257/E21.347, 257/E21.403, 257/E21.43, 257/E21.505, 257/E21.548, 257/E21.549, 257/E21.619, 257/E21.634, 257/E23.016, 257/E29.027, 257/E29.081, 257/E29.116, 257/E29.122, 257/E29.127, 438/486, 438/300, 438/487, 438/149, 438/166, 438/172, 438/299, 438/303, 438/479, 438/488, 438/138, 438/150, 438/197, 438/270, 438/271, 438/285, 438/296, 438/30, 438/301, 438/302, 438/304, 438/305, 438/426, 438/427, 438/436, 438/438, 438/478, 438/482, 438/483, 438/485, 438/489, 438/5, 438/511, 438/528, 438/589, 438/590, 438/639, 438/694, 438/745, 438/795, 438/931, 438/945, 438/973, 438/977, 349/129, 349/113, 349/114, 349/155, 349/156, 349/43, 349/122, 349/38, 349/107, 349/112, 349/133, 349/166, 349/174, 349/39, 349/47, 349/93, 349/100, 349/110, 349/111, 349/118, 349/123, 349/127, 349/130, 349/139, 349/141, 349/143, 349/158, 349/172, 349/173, 349/4, 349/46, 349/84, 349/94, 349/96, 349/66, 349/E21.102, 349/E21.123, 349/E21.131, 345/87, 345/94, 345/96, 345/54, 345/89, 345/95, 345/97
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A field effect transistor includes a semiconductor substrate having a protrusion with at least one inclined surface, a gate insulator disposed at least on a portion of the inclined surface, and a gate conductor disposed on the gate insulator, wherein the semiconductor substrate comprises doped regions sandwiching a channel region, wherein the at least one inclined surface has a first crystal orientation in the channel region, and the inclined surface has an included angle to a vertical plane with a second crystal orientation. The hole mobility and the electron mobility are substantially the same in the channel region having a crystalline orientation off from the (110) crystal orientation.

Claims

1. A field effect transistor, comprising:

a semiconductor substrate having a protrusion with a sloped incline surface, the semiconductor substrate comprising doped regions sandwiching a channel region;

a gate insulator disposed at least on a portion of the sloped incline surface;

a gate conductor disposed on the gate insulator;

wherein the arrangement of the semiconductor substrate, the gate insulator, and the gate conductor enables electron flow in a direction from a base of the semiconductor substrate to a distal end of the protrusion, wherein the distal end of the protrusion is a region furthest away from the base of the semiconductor substrate; and

wherein the sloped incline surface has a first crystal orientation in the channel region, and the sloped incline surface has an included angle to a vertical plane with a second crystal orientation.

2. The field effect transistor of claim 1, wherein the first crystal orientation is (551) and the second crystal orientation is (100).

3. The field effect transistor of claim 1, wherein the semiconductor substrate has a third crystal orientation of (110).

4. The field effect transistor of claim 1, wherein the included angle ranges from 9to 10 degrees.

5. The field effect transistor of claim 1, wherein the included angle ranges from 7to 9 degrees.

6. The field effect transistor of claim 1, wherein the included angle ranges from 5to 7 degrees.

7. The field effect transistor of claim 1, wherein the gate conductor traverses the protrusion horizontally.

8. The field effect transistor of claim 1, wherein the gate conductor surrounds the protrusion horizontally.

9. The field effect transistor of claim 1, wherein the protrusion has a trapezoid profile.

10. The field effect transistor of claim 1, wherein the protrusion has an inverted trapezoid profile.

11. The field effect transistor of claim 1, wherein the doped regions are disposed at a top of the protrusion and a bottom of the semiconductor substrate.

12. The field effect transistor of claim 1, wherein the gate insulator comprises an inclined portion on the sloped incline surface and a horizontal portion connected to the inclined portion.

13. The field effect transistor of claim 1, wherein the gate conductor comprises an inclined portion on the sloped incline surface and a horizontal portion connected to the inclined portion.

14. The field effect transistor of claim 1, wherein the doped regions have different conductivity types.