Semiconductor device

• US 9,136,333 B2
• Filed: 01/18/2012
• Issued: 09/15/2015
• Est. Priority Date: 07/14/2006
• Status: Expired due to Fees

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Aoki, Takaaki, Shiga, Tomofusa
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/352,415
• Publication Number:
  US 20120112273A1
• Time in Patent Office: 1,336 Days
• Field of Search: 257/327, 257/E27.06, 257328-346
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first conductive type, wherein the semiconductor substrate includes a first surface and a second surface opposite to the first surface, and the semiconductor substrate has a first portion and a second portion;

a drift layer having the first conductive type, wherein the drift layer is disposed in a surface portion of the first surface of the semiconductor substrate;

a vertical MOSFET disposed in the first portion of the semiconductor substrate; and

an accumulation FET for operating in an accumulation mode and disposed in the second portion of the semiconductor substrate, wherein

the vertical MOSFET includes;

the drift layer;

a base layer having a second conductive type, wherein the first conductive type is different from the second conductive type, wherein the base layer is disposed in the drift layer;

a source region having the first conductive type, wherein the source region is disposed in the base layer in such a manner that the source region is separated from the drift layer by the base layer;

a first gate insulation film disposed between the source region and the drift layer through the base layer;

a first gate electrode disposed on the first gate insulation film, wherein the first gate electrode provides a channel in a part of the base layer, which contacts the first gate insulation film;

a source electrode electrically coupling with the source region and the base layer; and

a drain electrode disposed on the second surface of the semiconductor substrate, and the accumulation FET includes;

a second trench disposed in the drift layer;

a second gate insulation film disposed on an inner wall of the second trench; and

a second gate electrode disposed on the second gate insulation film in the second trench, wherein a part of the drift layer contacting the second trench is coupled with the source electrode of the vertical MOSFET,

wherein the first gate electrode and the second gate electrode are independent from each other so that different voltages are applicable to the first gate electrode and the second gate electrode, respectively.

2. The semiconductor device according to claim 1, wherein

the MOSFET further includes a first trench penetrating through the source region and base layer and reaching the drift layer,

the first gate insulation film is disposed on an inner wall of the first trench,

the first gate electrode is disposed on the first gate insulation film in the first trench, and

the MOSFET is a trench gate type vertical MOSFET.

3. The semiconductor device according to claim 2, wherein

the first trench has a depth, which is equal to a second depth of the second trench.

4. The semiconductor device according to claim 1, wherein

the drift layer in the accumulation FET is pinched off by a depletion layer extending from the second gate insulation film to the drift layer when a gate voltage is not applied to the second gate electrode so that a current path between the source electrode and the drain electrode MOSFET is cut off.

5. The semiconductor device according to claim 1,

wherein the accumulation FET does not include the base layer.

6. The semiconductor device according to claim 1,

wherein the part of the drift layer contacting the second trench contacts the source electrode of the vertical MOSFET.