Semiconductor device having a trench gate structure and manufacturing method of the same

• US 9,136,335 B2
• Filed: 04/10/2012
• Issued: 09/15/2015
• Est. Priority Date: 04/12/2011
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Oosawa, Seigo, Taketani, Eiichi
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US13/443,059
• Publication Number:
  US 20120261714A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257330-336, 257/E29.201, 257E29257-E2926, 438/259, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a main surface and defining neighboring gate trench structures, each neighboring gate trench structure having a trench, each trench extending from the main surface of the semiconductor substrate and having a bottom wall;

a drift layer of a first conductivity type disposed at a portion in the semiconductor substrate adjacent to each trench;

an adjustment layer disposed on the bottom wall of each trench and having a first conductivity type impurity concentration higher than the drift layer;

a channel layer of a second conductivity type disposed at a portion of the semiconductor substrate adjacent to a sidewall of each trench and between the adjustment layer and the main surface, an entire region of the channel layer being shallower than the bottom wall of each trench relative to the main surface of the semiconductor substrate;

a source layer or an emitter layer disposed on a portion of the sidewall of each trench adjacent to the main surface, the source layer or the emitter layer having a first conductivity type impurity concentration higher than the drift layer, and

a high concentration body region disposed at a portion of the semiconductor substrate adjacent to the channel layer between the two neighboring trench gate structures, the high concentration body region extending to a position deeper than a lower end portion of the channel layer, the high concentration body region having a second conductivity type impurity concentration higher than the channel layer,

wherein the adjustment layer restricts the channel layer from extending in a depth direction of each trench of the neighboring gate structures.

2. The semiconductor device according to claim 1, wherein the high concentration body region extends to a position deeper than each trench.

3. The semiconductor device according to claim 1, further comprising:

a gate insulating layer including a sidewall insulating layer disposed on the sidewall of each trench and a bottom wall insulating layer disposed on the bottom wall of each trench,

wherein a thickness of the bottom wall insulating layer is larger than a thickness of the sidewall insulating layer and is smoothly increased along a curvature of the bottom wall of each trench.

4. The semiconductor device according to claim 1, wherein the entire region of the channel layer is located above the adjustment layer.