Shielded gate trench MOSFET package

• US 9,136,370 B2
• Filed: 06/03/2014
• Issued: 09/15/2015
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik, Su, Yi, Ng, Daniel, Calafut, Daniel, Bhalla, Anup
• Primary Examiner(s): AHMED, SELIM U
• Application Number:
  US14/294,520
• Publication Number:
  US 20140264571A1
• Time in Patent Office: 469 Days
• Field of Search: 257329-331, 257/409, 257/E21.418, 257/E21.419, 257/E29.027, 257/E29.262, 257/E21.41
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead.

Claims

1. A shielded gate field effect transistor comprising:

first and second active transistor regions;

a shield electrode connection region located between two active transistor regions, wherein the shield electrode connection region includes a plurality of shield electrode pickup trenches with each shield electrode pickup trench having a shield electrode contact formed therein and wherein the shield electrode contact is electrically isolated from source regions at the first and second active transistor regions; and

a shield electrode electrically connected to the shield electrode connection region.

2. The transistor of claim 1, wherein at least one of the plurality of shield electrode pickup trench is filled with heavily doped polysilicon.

3. A method for manufacturing a shielded gate trench field effect transistor, comprising:

a) providing an epitaxial layer of a first conductivity type on top of a substrate of a first conductivity type;

b) providing a body layer of a second conductivity type above the epitaxial layer;

c) providing a trench within the body layer and epitaxial layer, wherein the trench is lined with a dielectric layer;

d) providing a shield electrode within a lower portion of the trench, wherein the shield electrode is insulated from the epitaxial layer by the dielectric layer;

e) providing a gate electrode within the trench above the shield electrode, wherein the gate electrode is insulated from the shield electrode by an additional dielectric layer;

f) providing one or more source regions of a fourth conductivity type within a top surface of the body layer, wherein each source region is adjacent a sidewall of the trench;

g) providing a source pad above the body layer, wherein the source pad is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode, the source pad providing an external contact to the source region;

h) providing a gate pad above the body layer, wherein the gate pad is electrically connected to the gate electrode and insulated from the one or more source regions and the shield electrode, the gate pad providing an external contact to the gate electrode; and

i) providing a shield pad above the body layer, wherein the shield pad is electrically connected to the shield electrode and insulated from the one or more source regions and the gate electrode, the shield pad providing an external contact to the shield electrode.

4. The method of claim 3, further comprising providing a resistive element between the shield pad and a source lead that is electrically connected to the one or more source regions.

5. The method of claim 4, wherein providing the resistive element between the shield pad and the source lead includes placing a lumped resistive element between the shield pad and a source lead in a package.

6. The method of claim 5, wherein the lumped resistive element is an external resistive element.

7. The method of claim 6, wherein the external resistive element is a metal layer.

8. The method of claim 6, wherein the external resistive element is a polysilicon layer.

9. The method of claim 3, further comprising forming an internal resistive element between the shield electrode and the shield pad.

10. The method of claim 9, wherein the internal resistive element is a lumped resistor comprising polysilicon found within the shield electrode.

11. The method of claim 9, wherein the internal resistive element is a lumped resistor comprising polysilicon found within the gate electrode.

12. The method of claim 3, wherein the shield electrode is electrically connected to a shield electrode connection region located between two active regions, wherein the shield electrode connection region includes a plurality of shield electrode pickup trenches with each shield electrode pickup trench having a shield electrode contact formed therein.

13. The method of claim 12, wherein the lump resistance is implemented using heavily doped polysilicon to fill the shield electrode pickup trenches.

14. The method of claim 12, wherein the lumped resistance is located outside of a termination trench around one or more of the two active regions.

15. The method of claim 12, wherein the shield electrode pickup contacts are formed inside a termination region around one or more of the two active regions.

16. The method of claim 12 wherein a resistance value of the lumped resistance is determined by a length and/or width of the shield electrode pickup trenches and is adjustable by modifying the number of contacts.

17. The method of claim 12, wherein a number of shield electrode pickups trenches is selected to meet a desired lumped resistance target.