Device structure and methods of making high density MOSFETs for load switch and DC-DC applications

• US 9,136,380 B2
• Filed: 07/11/2014
• Issued: 09/15/2015
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Yilmaz, Hamza, Bobde, Madhur, Chang, Hong, Lee, Yeeheng, Calafut, Daniel, Kim, Jongoh, Lui, Sik, Chen, John
• Primary Examiner(s): Zhang, Yuanda
• Assistant Examiner(s): Maruf, Sheikh
• Application Number:
  US14/329,806
• Publication Number:
  US 20140339630A1
• Time in Patent Office: 431 Days
• Field of Search: 257133-137, 257/329, 257/334, 257/280, 257/341, 257/471, 257/332, 257/139, 257/E21.159, 257/E27.06, 257/E21.41, 257/E21.158, 257/E21.419, 257/E29.26, 257/E21.54, 257/E29.262, 257/E21.409, 438/270, 438/258, 438/589, 438/211, 438/257
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers that are formed along the sidewall of the gate caps. Additionally, the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The two-step gate oxide combined with the self-aligned source contacts allow for the production of devices with a pitch in the deep sub-micron level. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A MOSFET device, comprising:

a semiconductor substrate of a first conductivity type wherein the substrate includes a lightly doped epitaxial region in a top portion of the substrate;

a body region of a second conductivity type formed in a top portion of the semiconductor substrate, wherein the second conductivity type is opposite the first conductivity type;

a plurality of active device structures formed from the semiconductor substrate and body region, wherein each active device structure comprises a gate electrode insulated with a gate oxide, wherein an upper portion of the gate oxide is a thickness T₁ and a bottom portion of the gate oxide is a thickness T₂, wherein T₂ is greater than T₁;

one or more source regions of the first conductivity type formed in a top portion of the body region proximate the gate electrode;

an insulative gate cap formed over each gate electrode, wherein an insulating spacer is formed on the sidewalls of the gate cap and a conductive or semiconductor spacer is formed on the exposed side walls of the insulating spacer, an insulative layer over a top surface of the body region;

a conductive source metal layer formed over the insulative layer;

one or more electrical connections that connect the source metal layer with the one or more source regions, wherein the one or more electrical connections are spaced apart from the gate cap by the insulating spacer.

2. The MOSFET device of claim 1, wherein the conductive or semiconductor spacer is a polysilicon spacer.

3. The MOSFET device of claim 2, wherein the polysilicon spacer is doped with dopants of the first conductivity type.

4. The MOSFET device of claim 3, wherein the source region of the first conductivity type is omitted.

5. The MOSFET device of claim 1, further comprising a sub-body layer, wherein the sub-body layer is a lightly doped region of the second conductivity type formed below the bottom surface of the region.

6. The MOSFET device of claim 5, wherein the sub-body layer extends to a depth below the upper portion of the trench.

7. The MOSFET device of claim 1, further comprising one or more electrostatic discharge (ESD) protection features.

8. The MOSFET device of claim 1, further comprising one or more a gate pickup trenches.

9. The MOSFET device of claim 1, further comprising a Schottky contact.

10. The MOSFET device of claim 9, wherein the Schottky contact is a body clamp structure.