Semiconductor integrated circuit

• US 9,136,717 B2
• Filed: 03/04/2011
• Issued: 09/15/2015
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Hirano, Tetsuro, Kashima, Kyouichi, Fukushima, Yoshitaka, Ono, Masahiro
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): THOMAS, LUCY M
• Application Number:
  US13/040,891
• Publication Number:
  US 20110235224A1
• Time in Patent Office: 1,656 Days
• Field of Search: 361/56, 361/62
• US Class Current: 1/1
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits

Abstract

A circuit device connected between a neighboring pair of terminals in a semiconductor integrated circuit is protected from electrostatic damage due to a surge voltage when the surge voltage is applied between the neighboring pair of terminals. The semiconductor integrated circuit is formed to include terminals P0-P14, MOS transistors MN0-MN15 in diode connection, protection diode circuits HD0-HD14, MOS transistors T1-T14 for discharging electricity from batteries, a battery voltage detection control circuit and a clamp circuit for overvoltage protection. Each of the MOS transistors T1-T14 for discharging electricity from the batteries is connected between each neighboring pair of the terminals P0-P14 through wirings. Each of the MOS transistors MN1-MN14 in diode connection is connected between each neighboring pair of the terminals.

Claims

1. A semiconductor integrated circuit, comprising:

a plurality of terminals including at least three terminals forming neighboring pairs of terminals;

a plurality of switching devices arranged such that there is one switching device connected directly between each neighboring pair of terminals;

a battery voltage detection control circuit that detects a voltage between the terminals of each neighboring pair of terminals, wherein in response to the battery voltage detection control circuit detecting that a voltage across a first neighboring pair of terminals is higher than the voltage across a second neighboring pair of terminals, the battery voltage detection control circuit activates the switching device between the first neighboring pair of terminals to reduce the voltage at the first neighboring pair of terminals by discharging the voltage across the pair of terminals;

a plurality of first overvoltage protection devices connected in series, each overvoltage protection device being connected between a corresponding neighboring pair of terminals and protecting a corresponding one of the switching devices from an overvoltage applied between the corresponding neighboring pair of the terminals, wherein each overvoltage protection device is a N-type MOS transistor having a gate and a source connected to each other;

a plurality of second overvoltage protection devices, each of the second overvoltage protection devices being connected between every other terminal; and

a plurality of third overvoltage protection devices or circuits, each of the third overvoltage protection devices or circuits being connected to terminals that are not connected to the plurality of second overvoltage protection devices.

2. The semiconductor integrated circuit of claim 1, further comprising a power supply line and a clamp circuit, the power supply line being connected to one of the plurality of terminals, and the clamp circuit being connected between a ground and the power supply line and clamping an electric potential on the power supply line.

3. The semiconductor integrated circuit of claim 2, wherein the clamp circuit comprises a plurality of MOS transistors connected in series between the power supply line and the ground line, a gate and a source of each of the plurality of MOS transistors being connected to each other.

4. The semiconductor integrated circuit of claim 1, further comprising a power supply line and a plurality of protection diode circuits, the power supply line being connected to one of the plurality of terminals, and each of the protection diode circuits being connected to each of the plurality of terminals, respectively, wherein each of the plurality of protection diode circuits comprises a first diode and a second diode, the first diode being connected between the terminal and the power supply line, and the second diode being connected between the terminal and a ground.

5. A semiconductor integrated circuit, comprising:

a plurality of terminals including at least three terminals forming neighboring pairs of terminals aligned in a line, the terminals comprising odd number terminals that are placed at positions of odd numbers in the line and even number terminals that are placed at positions of even numbers in the line;

a plurality of switching devices, each one of the plurality of switching devices connected between a respective one of a corresponding neighboring pair of the terminals;

a battery voltage detection control circuit that detects a voltage between the terminals of each neighboring pair of terminals and that controls turning on/off of each corresponding switching device according to the voltage between the terminals of the corresponding neighboring pair of terminals to keep the voltages between each neighboring pair of terminals uniform with each other;

a plurality of first overvoltage protection devices connected in series, each of the first overvoltage protection devices being connected between a corresponding neighboring pair of the terminals and protecting a corresponding switching device from an overvoltage applied between the corresponding neighboring pair of terminals;

a plurality of second overvoltage protection devices, each of the second overvoltage protection devices being connected between a corresponding neighboring pair of even number terminals; and

a plurality of protection diode circuits, each of the protection diode circuits being connected only to a corresponding odd number terminal.

6. The semiconductor integrated circuit of claim 5, wherein each of the plurality of first overvoltage protection devices comprises a MOS transistor, a gate and a source of the MOS transistor being connected to each other.

7. The semiconductor integrated circuit of claim 5, further comprising a power supply line and a clamp circuit, the power supply line being connected to one of the plurality of terminals, and the clamp circuit being connected between a ground and the power supply line and clamping an electric potential on the power supply line.

8. The semiconductor integrated circuit of claim 7, wherein the clamp circuit comprises a plurality of MOS transistors connected in series between the power supply line and the ground line, a gate and a source of each of the plurality of MOS transistors being connected to each other.

9. The semiconductor integrated circuit of claim 5, further comprising a first additional one of the plurality of first overvoltage protection devices coupled in series between the plurality of first overvoltage protection devices and a power supply line, and a second additional one of the plurality of first overvoltage protection devices coupled in series between the plurality of first overvoltage protection devices and a ground line.

10. The semiconductor integrated circuit of claim 7, wherein each of the first plurality of overvoltage protection devices include each a N channel type MOS transistor having a drain connected to a first terminal and a gate and a source both connected to a second terminal of a terminal pair.

11. The semiconductor integrated circuit of claim 7, wherein the clamp circuit is coupled between the power supply line and the ground line formed of a plurality of P channel type MOS transistors coupled in series between the power supply line and the ground line, where each P channel type MOS transistor has a source and a gate coupled together.

12. The semiconductor integrated circuit of claim 5, further comprising an overvoltage protection circuit, the overvoltage protection circuit for protecting the semiconductor integrated circuit from electrostatic damage.

13. The semiconductor integrated circuit of claim 5, wherein each of the neighboring pairs of terminals has a first terminal and a second terminal, the semiconductor integrated circuit further comprises a plurality of P channel type MOS transistors coupled between the first terminal of each neighboring pair of terminals and the first terminal of a successive neighboring pair of terminals.

14. A semiconductor integrated circuit, comprising:

a plurality of terminal pairs, each terminal pair configured to be connected to a rechargeable battery;

a voltage detection circuit for detecting a voltage across each terminal pair; and

a plurality of discharge devices connected in series, each discharge device being connected across a terminal pair, wherein in response to the voltage detection circuit detecting that a voltage across a terminal pair is higher than a voltage across a neighboring terminal pair, the discharge device across the terminal pair discharges the rechargeable battery connected to the terminal pair to reduce the voltage at the terminal pair;

a plurality of first overvoltage protection devices connected in series, each overvoltage protection device being connected between a corresponding neighboring pair of terminals and protecting a corresponding one of the switching devices from an overvoltage applied between the corresponding neighboring pair of the terminals, wherein each overvoltage protection device is a N-type MOS transistor having a gate and a source connected to each other;

a plurality of second overvoltage protection devices, each of the second overvoltage protection devices being connected between every other terminal; and

a plurality of third protection devices or circuits, each of the third protection devices or circuits being connected to terminals that are not connected to the plurality of second overvoltage protection devices.

15. The semiconductor integrated circuit of claim 14, wherein the rechargeable battery is discharged to an extent that enables the voltage across the plurality of terminal pairs to remain uniform.

16. The semiconductor integrated circuit of claim 15, wherein each of the second overvoltage protection devices, protects a corresponding dicharge device from a voltage surge across the terminal pair.

17. The semiconductor integrated circuit of claim 16, wherein each of the third protection devices or circuits, is connected to one terminal of a the plurality of terminal pairs and to a power supply line for protecting the discharge devices from a voltage surge in a voltage supplied through the power supply line.

18. The semiconductor integrated circuit of claim 17, wherein the plurality of third protection devices or circuits each contain a first diode and a second diode, each first diode being connected to the one terminal of the terminal pair and to the power supply line to provide a first path between the one terminal and the supply line and each second diode being connected to the one terminal of the terminal pair and to ground to provide a second path between the one terminal to ground, the first path and the second path being selectively used by the voltage surge based on a polarity of the supplied voltage.

19. The semiconductor integrated circuit of claim 17, further comprising a clamp circuit, the clamp circuit for clamping the voltage supplied through the power supply line to a particular voltage when a surge voltage is included in the voltage supplied through the supply line.