Adaptive context disbursement for improved performance in non-volatile memory systems
First Claim
1. A controller circuit for a memory system including the controller circuit and one or more memory circuits, in which the controller circuit controls the transfer of data between the memory circuits and a host connected to the memory system and manages the storage of data on the memory circuits, the controller circuit comprising:
- a port by which the controller circuit is connectable to the one or more memory circuits through a bus structure;
a command processing section to issue high level commands for execution in the memory circuits;
a memory circuit interface module to issue in sequence by the port to one or more of the memory circuits a series of instruction derived from the high level commands; and
a queue manager to derive the series of instructions from the high level commands, wherein, when deriving a series of instruction from a set of high level data access commands, the queue manager modifies timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series derived from the set of high level data access commands.
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Accused Products
Abstract
A controller circuit for a non-volatile memory of one or more memory circuits is described. The controller is connectable by a port with the memory circuits through a bus structure and can operate the memory circuits according to one or more threads. The controller includes a command processing section to issue high level commands for execution in the memory circuits and a memory circuit interface module to issue in sequence by the port to the memory circuits a series of instruction derived from the high level commands. A queue manager on the controller derives the series of instructions from the high level commands. When deriving a series of instruction from a set of high level data access commands, the queue manager can modify the timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series.
42 Citations
16 Claims
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1. A controller circuit for a memory system including the controller circuit and one or more memory circuits, in which the controller circuit controls the transfer of data between the memory circuits and a host connected to the memory system and manages the storage of data on the memory circuits, the controller circuit comprising:
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a port by which the controller circuit is connectable to the one or more memory circuits through a bus structure; a command processing section to issue high level commands for execution in the memory circuits; a memory circuit interface module to issue in sequence by the port to one or more of the memory circuits a series of instruction derived from the high level commands; and a queue manager to derive the series of instructions from the high level commands, wherein, when deriving a series of instruction from a set of high level data access commands, the queue manager modifies timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series derived from the set of high level data access commands. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification