System level tools to support FPGA partial reconfiguration

• US 9,141,747 B1
• Filed: 11/11/2014
• Issued: 09/22/2015
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Orthner, Kent
• Primary Examiner(s): LEE, ERIC D
• Application Number:
  US14/538,697
• Time in Patent Office: 315 Days
• Field of Search: 716/139
• US Class Current: 1/1
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection

Abstract

Various embodiments of the present disclosure provide techniques for enabling a user to efficiently design a programmable logic device (PLD) capable of partial reconfiguration. In some implementations, a processor is configured to run a system level design tool and accepts, as inputs from a user, an identification of at least two personas to be used within a reconfigurable region of the PLD. The design tool defines one or more boundaries of a partial reconfig (PR) domain, the PR domain including a partitioned reconfigurable region of the PLD that is selectably configurable as any of the at least two personas. In some implementations, the PR domain includes at least one IP component configured to safely shut down at least one signal, the at least one signal originating from or directed toward an element of the PLD outside of the PR domain.

Claims

1. An apparatus for designing a reconfigurable programmable logic device (PLD), the apparatus comprising:

a processor configured to run a system level design tool, the processor accepting, as inputs from a user, an identification of at least two personas to be used within a partitioned reconfigurable region of the PLD, wherein;

the design tool (i) captures a list of the at least two personas, the list defining a superset of boundary interfaces that includes subsets of interfaces, each of the subsets of interfaces being associated with a respective one of the at least two personas;

(ii) ensures that each persona in the list has a compatible subset of interfaces; and

(iii) defines, as high-level interface descriptions, one or more boundaries of a partial reconfig (PR) domain inside the partitioned reconfigurable region of the PLD such that the PR domain is selectably reconfigurable as any of the at least two personas while at least one other portion of the PLD outside the partitioned reconfigurable region is still operating.

2. The apparatus of claim 1, wherein the design tool provides a graphical user interface (GUI), the GUI including a template that imposes the compatible subset of interfaces.

3. The apparatus of claim 1, wherein the design tool is configured to automatically instantiate one or both of an identification block and a reconfiguration status block inside at least one of the at least two personas.

4. The apparatus of claim 1, wherein the design tool is configured to support the simulation of partial reconfiguration.

5. The apparatus of claim 4, wherein the simulation includes simulating reconfiguration errors.

6. The apparatus of claim 5, wherein the simulation includes a functional coverage monitor, the functional coverage monitor being configured to inform the user when the simulation has covered all of a subset of cases to be tested.

7. The apparatus of claim 1, wherein the design tool is configured to allow a host PC to reconfigure the PR domain directly, without requiring the use of an embedded processor or state machine in the FPGA.

8. The apparatus of claim 1, wherein the design tool is configured to store events related to partial reconfiguration for post-failure debug.

9. A method for designing a reconfigurable programmable logic device (PLD), the method comprising:

receiving, at a processor configured to run a system level design tool, as inputs from a user, an identification of at least two personas to be used within a partitioned reconfigurable region of the PLD, wherein the design tool captures a list of the at least two personas, the list defining a superset of boundary interfaces that includes subsets of interfaces, each of the subsets of interfaces being associated with a respective one of the at least two personas and ensures that each persona in the list has a compatible subset of interface; and

defining, with the design tool, as high-level interface descriptions, one or more boundaries of a partial reconfig (PR) domain inside the partitioned reconfigurable region of the PLD such that the PR domain is selectably reconfigurable as any of the at least two personas while at least one other portion of the PLD outside the partitioned reconfigurable region is still operating.

10. The method of claim 9, further comprising automatically instantiating, with the design tool, one or both of an identification block and a reconfiguration status block inside at least one of the at least two personas.

11. The method of claim 9, wherein the design tool is configured to support the simulation of partial reconfiguration.

12. The method of claim 11, wherein the simulation includes simulating reconfiguration errors.

13. The method of claim 12, wherein the simulation includes a functional coverage monitor, the functional coverage monitor being configured to inform the user when the simulation has covered all of a subset of cases to be tested.

14. The method of claim 9, wherein the design tool is configured to allow a host PC to reconfigure the PR domain directly, without requiring the use of an embedded processor or state machine in the FPGA.

15. The method of claim 9, wherein the design tool is configured to store events related to partial reconfiguration for post-failure debug.

16. A non-transitory computer-readable storage medium having stored thereon instructions which, when executed by a processor, cause the processor to perform operations, the operations comprising:

receiving, at a processor configured to run a system level design tool, as inputs from a user, an identification of at least two personas to be used within a partitioned reconfigurable region of the PLD, wherein the design tool captures a list of the at least two personas, the list defining a superset of boundary interfaces that includes subsets of interfaces, each of the subsets of interfaces being associated with a respective one of the at least two personas and ensures that each persona in the list has a compatible subset of interface; and

defining, high-level interface descriptions, with the design tool, one or more boundaries of a partial reconfig (PR) domain inside the partitioned reconfigurable region of the PLD such that the PR domain is selectably reconfigurable as any of the at least two personas while at least one other portion of the PLD outside the partitioned reconfigurable region is still operating.

17. The storage medium of claim 16, wherein the operations further comprise automatically instantiating, with the design tool, one or both of an identification block and a reconfiguration status block inside at least one of the at least two personas.

18. The storage medium of claim 16, wherein the design tool is configured to allow a host PC to reconfigure the PR domain directly, without requiring the use of an embedded processor or state machine in the FPGA.

19. The storage medium of claim 16, wherein the design tool is configured to store events related to partial reconfiguration for post-failure debug.