Flash multiple-pass write with accurate first-pass write

• US 9,142,303 B2
• Filed: 02/25/2015
• Issued: 09/22/2015
• Est. Priority Date: 04/04/2011
• Status: Active Grant

• Current Assignee: SK Hynix Memory Solutions Incorporated (SK Hynix Inc.)
• Original Assignee: SK Hynix Memory Solutions Incorporated (SK Hynix Inc.)
• Inventors: Lee, Meng-Kun, Wu, Yingquan
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/631,448
• Publication Number:
  US 20150235707A1
• Time in Patent Office: 209 Days
• Field of Search: 365/185.19, 365/185.14, 365/185.28
• US Class Current: 1/1
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.

Claims

1. A method, comprising:

receiving, at a Flash controller, an instruction to write to a location in a Flash memory;

performing an accurate coarse write on the location, including by configuring a level placement setting, associated with defining what voltage ranges correspond to what bit values, to be a first value; and

after the accurate coarse write is performed on the location;

reading the location to obtain a read-back bit value;

determining if the read-back bit value is a correct bit value;

in the event;

(1) it is determined that the read-back bit value is not the correct bit value and (2) a voltage level stored by the location is greater than a voltage range corresponding to the correct bit value per the level placement setting being set to the first value, setting the level placement setting to be a third value, wherein the level placement setting when set to the third value causes the stored voltage level to be within the voltage range corresponding to the correct bit value; and

in the event it is determined that the read-back value is the correct value, performing a fine write on the location, including by configuring the level placement setting to be a second value.

2. The method of claim 1, wherein the method is performed by a semiconductor device, including one or more of the following:

an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an embedded microprocessor, or an Advanced RISC Machine (ARM) embedded core.

3. The method of claim 1, wherein in the event:

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is greater than the voltage range corresponding to the correct bit value, the method further includes not performing any additional program pulses.

4. The method of claim 1 further comprising after the accurate coarse write is performed on the location, in the event:

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is less than the voltage range corresponding to the correct bit value, the method further includes performing one or more additional program pulses in order to bring the voltage level stored by the location to a level that is within the voltage range corresponding to the correct bit value per the level placement setting being set to the first value.

5. The method of claim 1, wherein an accurate coarse write is performed on a first location, followed by an accurate coarse write performed on a second location, following by a fine write performed on the first location, followed by a fine write performed on the second location.

6. A system, comprising:

a Flash memory; and

a Flash controller configured to;

receiving, at the Flash controller, an instruction to write to a location in the Flash memory;

performing an accurate coarse write on the location, including by configuring a level placement setting, associated with defining what voltage ranges correspond to what bit values, to be a first value; and

after the accurate coarse write is performed on the location;

reading the location to obtain a read-back bit value;

determining if the read-back bit value is a correct bit value;

in the event;

(1) it is determined that the read-back bit value is not the correct bit value and (2) a voltage level stored by the location is greater than a voltage range corresponding to the correct bit value per the level placement setting being set to the first value, setting the level placement setting to be a third value, wherein the level placement setting when set to the third value causes the stored voltage level to be within the voltage range corresponding to the correct bit value; and

in the event it is determined that the read-back value is the correct value, performing a fine write on the location, including by configuring the level placement setting to be a second value.

7. The system of claim 6, wherein the Flash controller includes a semiconductor device, including one or more of the following:

an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an embedded microprocessor, or an Advanced RISC Machine (ARM) embedded core.

8. The system of claim 6, wherein in the event:

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is greater than the voltage range corresponding to the correct bit value, the Flash controller is configured to not perform any additional program pulses.

9. The system of claim 6, wherein the Flash controller is further configured to:

after the accurate coarse write is performed on the location, in the event;

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is less than the voltage range corresponding to the correct bit value, perform one or more additional program pulses in order to bring the voltage level stored by the location to a level that is within the voltage range corresponding to the correct bit value per the level placement setting being set to the first value.

10. The system of claim 6, wherein an accurate coarse write is performed on a first location, followed by an accurate coarse write performed on a second location, following by a fine write performed on the first location, followed by a fine write performed on the second location.

11. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

receiving, at a Flash controller, an instruction to write to a location in a Flash memory;

performing an accurate coarse write on the location, including by configuring a level placement setting, associated with defining what voltage ranges correspond to what bit values, to be a first value; and

after the accurate coarse write is performed on the location;

reading the location to obtain a read-back bit value;

determining if the read-back bit value is a correct bit value;

in the event;

(1) it is determined that the read-back bit value is not the correct bit value and (2) a voltage level stored by the location is greater than a voltage range corresponding to the correct bit value per the level placement setting being set to the first value, setting the level placement setting to be a third value, wherein the level placement setting when set to the third value causes the stored voltage level to be within the voltage range corresponding to the correct bit value; and

in the event it is determined that the read-back value is the correct value, performing a fine write on the location, including by configuring the level placement setting to be a second value.

12. The computer program product of claim 11, wherein in the event:

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is greater than the voltage range corresponding to the correct bit value, the computer program product further includes computer instructions for not performing any additional program pulses.

13. The computer program product of claim 11 further comprising computer instructions for after the accurate coarse write is performed on the location, in the event:

(1) it is determined that the read-back bit value is not the correct bit value and (2) the voltage level stored by the location is less than the voltage range corresponding to the correct bit value, the method further includes performing one or more additional program pulses in order to bring the voltage level stored by the location to a level that is within the voltage range corresponding to the correct bit value per the level placement setting being set to the first value.

14. The computer program product of claim 11, wherein an accurate coarse write is performed on a first location, followed by an accurate coarse write performed on a second location, following by a fine write performed on the first location, followed by a fine write performed on the second location.