Semiconductor device and method of manufacturing a semiconductor device with a continuous silicate glass structure

• US 9,142,401 B2
• Filed: 06/16/2014
• Issued: 09/22/2015
• Est. Priority Date: 05/16/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Susiti, Alexander, Zundel, Markus, Ploss, Reinhard
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US14/305,359
• Publication Number:
  US 20140291816A1
• Time in Patent Office: 463 Days
• Field of Search: 257/330, 257/295, 257/E21.651, 257/E27.091, 257/E29.027, 257/E29.066, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a semiconductor device includes forming a continuous silicate glass structure over a first surface of a semiconductor body, including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure.

Claims

1. A semiconductor device, comprising:

a semiconductor body including a first surface;

a continuous silicate glass structure over the first surface; and

wherein

a part of the continuous glass structure in an area at least partially surrounding the active area includes a concentration of at least one of phosphor and boron that decreases by at least a factor of two between a first side and a second side of the continuous glass structure, wherein the second side is closer to the first surface of the semiconductor body than the first side.

2. The semiconductor device of claim 1, wherein an implantation dose of the at least one of phosphor and boron is in a range between 5×

10¹⁶ cm<sup>−

2</sup> and 5×

10¹⁷ cm<sup>−

2</sup>.

3. The semiconductor device of claim 1, wherein the part of the continuous glass structure excludes an active area and includes an area at least partially surrounding the active area.

4. The semiconductor device of claim 1, wherein the part of the continuous glass structure includes an overall area of the continuous glass structure.

5. The semiconductor device of claim 1, wherein the continuous glass structure includes an undoped silicate glass layer on top and/or at the bottom.

6. The semiconductor device of claim 1, wherein the semiconductor device is one of an insulated gate bipolar transistor, diode, silicon controlled rectifier, and metal-oxide-semiconductor field-effect transistor.

7. A semiconductor device, comprising:

a semiconductor body including a first surface;

a continuous silicate glass layer stack over the first surface; and

wherein

the continuous silicate glass layer stack includes at least one BPSG layer and one PSG layer over an active area of the semiconductor body and over a junction termination area surrounding the active area.

8. The semiconductor device of claim 7, wherein the continuous silicate glass layer stack further includes at least one of BSG and USG.