Methods of fabricating semiconductor devices

• US 9,142,461 B2
• Filed: 05/28/2014
• Issued: 09/22/2015
• Est. Priority Date: 03/22/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Do, Jinho, Lim, Hajin, Kim, WeonHong, Hong, Kyungil, Song, Moonkyun
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US14/289,076
• Publication Number:
  US 20140273382A1
• Time in Patent Office: 482 Days
• Field of Search: 438/285, 438/229, 438/199, 438/222, 438/217, 438/602, 438/518, 438/592, 438/197, 438/515, 438/510, 438/786, 438/157, 438/216, 257/411, 257/204, 257/369, 257/19, 257/75, 257/288
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/2822 with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

preparing a substrate including a first region and a second region;

forming a silicon-germanium layer on a first sub-region of the first region and a second sub-region of the second region;

forming a nitrogen impurity region in an upper portion of the silicon-germanium layer;

forming a first gate dielectric layer on the first region and the second region including the nitrogen impurity region;

heat treating the first gate dielectric layer after forming the first gate dielectric layer;

removing the first gate dielectric layer in the second region;

forming a second gate dielectric layer on the first region and the second region including the nitrogen impurity region; and

forming a third gate dielectric layer between the first gate dielectric layer and the second gate dielectric layer on the first region including the nitrogen impurity region and under the second gate dielectric layer on the second region including the nitrogen impurity region,

wherein the second and third gate dielectric layers are thinner than the first gate dielectric layer.

2. The method of claim 1, wherein the nitrogen impurity region is formed before the heat treating the first gate dielectric layer.

3. The method of claim 1, wherein the second gate dielectric layer includes a high-k dielectric layer having a higher dielectric constant than that of a silicon oxide layer.

4. The method of claim 3, wherein the third gate dielectric layer includes a silicon oxynitride layer.

5. The method of claim 1, wherein the nitrogen impurity region has a nitrogen concentration of about 5×

10¹⁰ to about 2×

10¹⁶ atm/cm³.

6. The method of claim 1, wherein the second gate dielectric layer includes at least one of hafnium, tantalum, and silicon.