Passivation structure of fin field effect transistor

• US 9,142,474 B2
• Filed: 10/07/2013
• Issued: 09/22/2015
• Est. Priority Date: 10/07/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Yu, Shih, Chi-Yuan, Yeh, Ling-Yen, Wann, Clement Hsingjen
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US14/047,804
• Publication Number:
  US 20150097239A1
• Time in Patent Office: 715 Days
• Field of Search: 257/18, 257/19, 257/20, 257/15, 257/24, 257/622, 257/623, 257/618, 257/192, 438/FOR.432, 438/FOR.487, 438/39, 438/41, 438/42, 438/44, 438/700, 438/978, 438/590, 438/283, 438/938, 438/285, 438/142
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02318 post-treatment
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material.

Claims

1. A fin field effect transistor (FinFET) comprising:

a substrate comprising a major surface;

a fin structure protruding from the major surface comprising;

a lower fin portion comprising a first semiconductor material having a first lattice constant;

an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant;

a middle fin portion between the lower fin portion and upper fin portion, wherein the middle fin portion comprises a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and

a passivation structure surrounding the fin structure comprising;

a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material;

an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and

a middle passivation portion between the lower passivation portion and upper passivation portion, wherein the middle passivation portion surrounding the middle fin portion comprises a third oxynitride of the third semiconductor material.

2. The FinFET of claim 1, the passivation structure further comprising:

a top passivation portion on an apex of the upper fin portion, wherein the top passivation portion comprises a fourth oxynitride of the second semiconductor material.

3. The FinFET of claim 2, wherein a ratio of a first N/O ratio of the fourth oxynitride is equal to or greater than a second N/O ratio of the second oxynitride.

4. The FinFET of claim 3, wherein a ratio of the first N/O ratio to the second N/O ratio is from about 1 to about 1.3.

5. The FinFET of claim 1, wherein the middle passivation portion further extends into a portion surrounding the lower fin portion.

6. The FinFET of claim 1, wherein a first height of the middle passivation portion is equal to or greater than a second height of the middle fin portion.

7. The FinFET of claim 6, wherein a ratio of the first height to the second height is from about 1 to about 1.2.

8. A fin field effect transistor (FinFET) comprising:

a substrate comprising a major surface;

a fin structure protruding from the major surface comprising;

a lower fin portion comprising a first semiconductor material having a first lattice constant;

an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant;

a middle fin portion between the lower fin portion and upper fin portion, wherein the middle fin portion comprises a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant;

a passivation structure surrounding the fin structure comprising;

a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material;

an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material;

a middle passivation portion between the lower passivation portion and upper passivation portion, wherein the middle passivation portion surrounding the middle fin portion comprises a third oxynitride of the third semiconductor material; and

an isolation structure surrounding the passivation structure, wherein a top surface of the isolation structure is higher than or lower than an interface of the upper passivation portion and middle passivation portion.

9. The FinFET of claim 8, the passivation structure further comprising:

a top passivation portion on an apex of the upper fin portion, wherein the top passivation portion comprises a fourth oxynitride of the second semiconductor material.

10. The FinFET of claim 9, wherein a ratio of a first N/O ratio of the fourth oxynitride is equal to or greater than a second N/O ratio of the second oxynitride.

11. The FinFET of claim 10, wherein a ratio of the first N/O ratio to the second N/O ratio is from about 1 to about 1.3.

12. The FinFET of claim 8, wherein the middle passivation portion further extends into a portion surrounding the lower fin portion.

13. The FinFET of claim 8, wherein a first height of the middle passivation portion is equal to or greater than a second height of the middle fin portion.

14. The FinFET of claim 13, wherein a ratio of the first height to the second height is from about 1 to about 1.2.

15. The FinFET of claim 8, wherein a height difference between the top surface and the interface is from about −

5 nm to about 20 nm.

16. A method of fabricating a fin field effect transistor, comprising:

providing a silicon substrate;

epi-growing a silicon germanium layer over the silicon substrate;

epi-growing a germanium layer over the silicon germanium layer;

forming a plurality of trenches that extends through the germanium layer, silicon germanium layer, and into the silicon substrate to form a fin structure; and

forming a passivation structure surrounding the fin structure, wherein the passivation structure comprises a lower passivation portion surrounding the silicon comprising silicon oxynitride, a middle passivation portion surrounding the silicon germanium layer comprising silicon germanium oxynitride, and an upper passivation portion surrounding the germanium layer comprising germanium oxynitride.

17. The method of claim 16, wherein the step of forming a passivation structure surrounding the fin structure is performed using a rapid thermal oxidation process followed by a decoupled plasma nitridation process.

18. The method of claim 17, wherein the step of forming a passivation structure surrounding the fin structure further comprises:

using a post nitridation anneal process after the decoupled plasma nitridation process.

19. The method of claim 16, wherein the step of forming a passivation structure surrounding the fin structure is performed using a rapid thermal oxidation process followed by a rapid thermal nitridation process.

20. The method of claim 19, wherein the rapid thermal nitridation process is performed at a temperature of about 400°

C. to about 800°

C.