Method of wire bonding over active area of a semiconductor circuit

• US 9,142,527 B2
• Filed: 10/29/2007
• Issued: 09/22/2015
• Est. Priority Date: 10/15/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lee, Jin-Yuan, Chen, Ying-Chih, Lin, Mou-Shiung
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US11/926,156
• Publication Number:
  US 20080045003A1
• Time in Patent Office: 2,885 Days
• Field of Search: 257750-766, 257/784, 257/E23.02, 438/623
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. A method for wirebonding to an integrated circuit die, comprising:

providing a semiconductor substrate, an active device in said semiconductor substrate, a first interconnect conductive layer coupled to said semiconductor substrate, an interlayer dielectric layer on said first interconnect conductive layer and said semiconductor substrate, and a second interconnect conductive layer on said interlayer dielectric layer;

providing a passivation layer directly on said interlayer dielectric layer, directly on sidewalls and directly on a surface of said second interconnect conductive layer, wherein a first opening in said passivation layer exposes a first contact point of a first conductive interconnect of said second interconnect conductive layer, and said first contact point is within said first opening, wherein said passivation layer comprises a nitride;

depositing a stress-absorbing buffer layer directly on said passivation layer;

exposing said first opening in said passivation layer through a second opening in said stress-absorbing buffer layer to expose a surface of said passivation layer opposite said first conductive interconnect and sidewalls of said passivation layer;

providing a conductive structure directly on a surface of said stress-absorbing buffer layer opposite said passivation layer, directly on sidewalls of said stress-absorbing buffer layer, directly on said exposed surface of said passivation layer opposite said first conductive interconnect and directly on sidewalls of said passivation layer, wherein said conductive structure is directly coupled to said passivation layer through said second opening in said stress-absorbing buffer layer and directly coupled to said first conductive interconnect at said first contact point through said first opening of said passivation layer, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer having a thickness of approximately 5000 angstroms on said glue layer, an electroplated copper layer having a thickness greater than 1 micrometer on said copper-containing seed layer, a nickel layer having a thickness in the range of 1 to 2 micrometers on said electroplated copper layer, and a gold layer having a thickness greater than 0.1 micrometer on said nickel layer; and

forming a wire bond on a second contact point of said conductive structure, wherein said wire bond is coupled to said second contact point, wherein said second contact point is coupled to said first contact point through said first opening, wherein a first contact area between said first contact point and said conductive structure has a width smaller than that of a second contact area between said second contact point and said wire bond, wherein said second contact area is aligned with said active device a second conductive interconnect of said first interconnect conductive layer and a third conductive interconnect of said second interconnect conductive layer, wherein said first conductive interconnect comprises a portion spaced apart from said third conductive interconnect, wherein said second contact area is further-aligned with a first sidewall of said second conductive interconnect and a second sidewall of said second conductive interconnect, wherein said first sidewall is opposite to said second sidewall, and wherein said second contact area is further aligned with a third sidewall of said third conductive interconnect, wherein said third sidewall is opposite to a fourth sidewall of said third conductive interconnect, and wherein said second contact area is aligned with said first conductive interconnect of said second interconnect conductive layer.

2. The method of claim 1, wherein said passivation layer further comprises an oxide.

3. The method of claim 1, wherein a second opening in said passivation layer is over a third contact point of said third conductive interconnect, and said third contact point is within said second opening, wherein said first contact point is coupled to said third contact point through said conductive structure.

4. The method of claim 1 further comprising said providing said conductive structure on said first contact point and over said passivation layer.

5. The method of claim 1, wherein said second contact point is aligned with a first sloped sidewall of said polymer layer and aligned with a second sloped sidewall of said polymer layer, in which the first sloped sidewall is opposite said second sloped sidewall of said polymer layer.

6. The method of claim 1, wherein said providing said conductive structure further comprises providing a gold layer having a hardness of 15-150 Vickers Hardness (HV).

7. The method of claim 6, wherein said providing said conductive structure further comprises providing a gold layer that has been annealed at a temperature in the range of 120-350°

C.

8. A method for wirebonding to an integrated circuit die, comprising:

providing a semiconductor substrate, an active device in said semiconductor substrate, a first interconnect conductive layer coupled to said semiconductor substrate, an interlayer dielectric layer on said first interconnect conductive layer and said semiconductor substrate, wherein said interlayer dielectric layer comprises a low-k material comprising one of a polyarylene ether, a polyarylene, a polybenzoxazole, and a dielectric having a Si_wC_xO_yH_z composition, and a second interconnect conductive layer on said interlayer dielectric layer;

providing a passivation layer directly on said interlayer dielectric layer and directly on sidewalls and directly on a surface of said second interconnect conductive layer, wherein a first opening in said passivation layer exposes a first contact point of a first conductive interconnect of said second interconnect conductive layer, and said first contact point is within said first opening;

depositing a stress-absorbing buffer layer directly on said passivation layer, wherein a second opening in said stress-absorbing buffer layer exposes said first contact point, a surface of said passivation layer opposite said first conductive interconnect and sidewalls of said passivation layer;

providing a conductive structure directly on a surface of said stress-absorbing buffer layer opposite said passivation layer, directly on sidewalls of said stress-absorbing buffer layer, directly on said exposed surface of said passivation layer opposite said first conductive interconnect, directly on sidewalls of said passivation layer, and directly on said first contact point, wherein said conductive structure is directly coupled to said first conductive interconnect at said first contact point and directly coupled to said passivation through said second opening of said stress-absorbing buffer layer; and

forming a wire bond on a second contact point of said conductive structure, wherein said wire bond is coupled to said second contact point, wherein said second contact point is coupled to said first contact point through said second opening, wherein a first contact area between said second contact point and said wire bond is aligned with said active device, and wherein said first contact area is aligned with said first conductive interconnect of said second interconnect conductive layer.

9. The method of claim 8, wherein said passivation layer further comprises an oxide.

10. The method of claim 8, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer on said glue layer and an electroplated copper layer on said copper-containing seed layer.

11. The method of claim 8, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer and a nickel layer on said electroplated copper layer.

12. The method of claim 8, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer, a nickel layer on said electroplated copper layer and a wirebondable layer on said nickel layer.

13. The method of claim 8, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer and a wirebondable layer over said electroplated copper layer.

14. The method of claim 8, wherein said providing said conductive structure comprises providing a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer and a gold layer over said electroplated copper layer.

15. The method of claim 8, wherein a third opening in said passivation layer is over a third contact point of a second conductive interconnect of said second interconnect conductive layer, and said third contact point is within said third opening, wherein a fourth opening in said stress-absorbing buffer layer exposes said third contact point, wherein said first conductive interconnect comprises a portion spaced apart from said second conductive interconnect, wherein said conductive structure is coupled to said third contact point through said fourth opening, wherein said first contact point is coupled to said third contact point through said conductive structure.

16. The method of claim 8, wherein said first contact area has a width greater than that of a second contact area between said first contact point and said conductive structure.

17. The method of claim 8, wherein said first contact area is further aligned with a second conductive interconnect of said first interconnect conductive layer and aligned with a third conductive interconnect of said second interconnect conductive layer, wherein said first conductive interconnect comprises a portion spaced apart from said third conductive interconnect, wherein said first contact area is further aligned with a first sidewall of said second conductive interconnect and aligned with a second sidewall of said second conductive interconnect, wherein said first sidewall is opposite to said second sidewall, and wherein said first contact area is further aligned with a third sidewall of said third conductive interconnect and aligned with a fourth sidewall of said third conductive interconnect, wherein said third sidewall is opposite to said fourth sidewall.

18. The method of claim 8, wherein said second contact point is aligned with a first sloped sidewall of said stress-absorbing buffer layer and aligned with a second sloped sidewall of said stress-absorbing buffer layer, in which the first sloped sidewall is opposite said second sloped sidewall of said stress-absorbing buffer layer.