Semiconductor memory device

• US 9,142,549 B2
• Filed: 05/30/2013
• Issued: 09/22/2015
• Est. Priority Date: 03/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/905,223
• Publication Number:
  US 20130256658A1
• Time in Patent Office: 845 Days
• Field of Search: 257/43, 257/57, 257/68, 257/71, 257/296, 257/369
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared.

Claims

1. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory cell,

wherein the first to third wirings intersect with the fourth wiring,

wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein one of a source and a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are connected to the fourth wiring,

wherein the other of the source and the drain of the second transistor is connected to the third wiring,

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor, and

wherein it is configured that at least three different potentials are applied to the third wiring.

2. The semiconductor memory device according to claim 1, wherein the conductivity type of the second transistor is p-type.

3. The semiconductor memory device according to claim 1, wherein the first transistor comprises an oxide semiconductor.

4. The semiconductor memory device according to claim 3, wherein the oxide semiconductor contains zinc and indium.

5. The semiconductor memory device according to claim 1, wherein the second transistor comprises a single crystal silicon semiconductor.

6. The semiconductor memory device according to claim 1, wherein the first transistor is formed over the second transistor.

7. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory cell,

wherein the first to third wirings intersect with the fourth wiring,

wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein one of a source and a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are connected to the fourth wiring,

wherein the other of the source and the drain of the second transistor is connected to the third wiring,

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor,

wherein it is configured that a first potential, a second potential and a third potential are applied to the third wiring, and

wherein the first potential is lower than the second potential and the second potential is lower than the third potential.

8. The semiconductor memory device according to claim 7, wherein the conductivity type of the second transistor is p-type.

9. The semiconductor memory device according to claim 7, wherein the first transistor comprises an oxide semiconductor.

10. The semiconductor memory device according to claim 9, wherein the oxide semiconductor contains zinc and indium.

11. The semiconductor memory device according to claim 7, wherein the second transistor comprises a single crystal silicon semiconductor.

12. The semiconductor memory device according to claim 7, wherein the first transistor is formed over the second transistor.

13. A semiconductor device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory cell,

wherein the first and the second wirings intersect with the fourth wiring,

wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor,

wherein one of a source and a drain of the first transistor is connected to a gate of the second transistor and one electrode of the first capacitor,

wherein a gate of the first transistor is connected to the first wiring,

wherein the other electrode of the first capacitor is connected to the second wiring,

wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are connected to the fourth wiring,

wherein the other of the source and the drain of the second transistor is connected to the third wiring,

wherein a conductivity type of the first transistor is different from a conductivity type of the second transistor, and

wherein it is configured that at least two different potentials are applied to the third wiring.

14. The semiconductor memory device according to claim 13, wherein the conductivity type of the second transistor is p-type.

15. The semiconductor memory device according to claim 13, wherein the first transistor comprises an oxide semiconductor.

16. The semiconductor memory device according to claim 15, wherein the oxide semiconductor contains zinc and indium.

17. The semiconductor memory device according to claim 13, wherein the second transistor comprises a single crystal silicon semiconductor.

18. The semiconductor memory device according to claim 13, wherein the first transistor is formed over the second transistor.