Semiconductor device

• US 9,142,555 B2
• Filed: 11/20/2014
• Issued: 09/22/2015
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yoshida, Yoshinori, Kato, Hirokazu, Kachi, Tsuyoshi, Furuya, Keisuke
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US14/548,311
• Publication Number:
  US 20150145025A1
• Time in Patent Office: 306 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 2224/8485 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/36 : Structure, shape, material or disposition of the strap connectors prior to the connecting process
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4175 : for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/665 : using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66659 : with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66689 : with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of unit MISFET elements formed in a first MISFET formation region of a main surface of the semiconductor substrate and coupled in parallel to each other;

an interconnect line structure formed over the semiconductor substrate and having a first interconnect line layer, and a second interconnect line layer located over the first interconnect line layer; and

a back surface electrode formed over a back surface of the semiconductor substrate opposite to the main surface,

wherein each of the unit MISFET elements has a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate located between the source region and the drain region via a gate insulating film,

wherein the first interconnect line layer of the interconnect line structure includes a first source interconnect line, and a first gate interconnect line,

wherein the second interconnect line layer of the interconnect line structure includes a second source interconnect line, and a second gate interconnect line,

wherein each of the first source interconnect line and the first gate interconnect line has a thickness smaller than a thickness of each of the second source interconnect line and the second gate interconnect line,

wherein the respective drain regions of the unit MISFET elements are electrically coupled to the back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate to be electrically coupled to each other,

wherein the respective source regions of the unit MISFET elements are electrically coupled to each other via the first source interconnect line and the second source interconnect line,

wherein the respective gate electrodes of the unit MISFET elements are electrically coupled to each other via the first gate interconnect line and electrically coupled to the second gate interconnect line via the first gate interconnect line, and

wherein the first gate interconnect line extends over the plug.

2. The semiconductor device according to claim 1,

wherein the first gate interconnect line extends over the plug in a first direction as an extending direction of each of the gate electrodes.

3. The semiconductor device according to claim 2,

wherein the plug extends in the first direction between the gate electrodes adjacent to each other with the drain regions being interposed therebetween.

4. The semiconductor device according to claim 3,

wherein, over the first MISFET formation region, the first gate interconnect line integrally includes a portion extending in the first direction, and a portion extending in a second direction crossing the first direction, and

wherein the portion of the first gate interconnect line extending in the first direction extends over the plug in the first direction.

5. The semiconductor device according to claim 4,

wherein the first source interconnect line is divided into a plurality of discrete source interconnect lines with the first gate interconnect line being interposed therebetween,

wherein, over the respective source regions of the unit MISFET elements, the discrete source interconnect lines are placed,

wherein the second source interconnect line is placed so as to cover the discrete source interconnect lines, and

wherein the discrete source interconnect lines are electrically coupled to each other via the second source interconnect line.

6. The semiconductor device according to claim 5,

wherein, in plan view, each of the discrete source interconnect lines is surrounded by the first gate interconnect line.

7. The semiconductor device according to claim 6,

wherein the discrete source interconnect lines extend also over the gate electrodes.

8. The semiconductor device according to claim 7,

wherein each of the unit MISFET elements further includes a field plate electrode,

wherein the discrete source interconnect lines extend also over the field plate electrodes, and

wherein the field plate electrodes are electrically coupled to the discrete source interconnect lines.

9. The semiconductor device according to claim 8,

wherein each of the field plate electrodes extends from over a part of the drain region to over a part of the gate electrode via an insulating film.

10. The semiconductor device according to claim 6,

wherein the first gate interconnect line has a portion extending along an outer periphery of the first MISFET formation region,

wherein the second gate interconnect line has a portion extending along the outer periphery of the first MISFET formation region, and

wherein, in plan view, the portion of the first gate interconnect line extending along the outer periphery of the first MISFET formation region overlaps the portion of the second gate interconnect line extending along the outer periphery of the first MISFET formation region.

11. The semiconductor device according to claim 1,

wherein the second source interconnect line forms a source pad, and

wherein the second gate interconnect line forms a gate pad.

12. The semiconductor device according to claim 1,

wherein each of the first interconnect line layer and the second interconnect line layer of the interconnect line structure has no interconnect line coupled to the drain regions of the unit MISFET elements.

13. The semiconductor device according to claim 1,

wherein the unit MISFET elements are unit LDMOSFET elements.

14. The semiconductor device according to claim 1,

wherein the plug is made of a metal film embedded in the trench of the semiconductor substrate.

15. The semiconductor device according to claim 1,

wherein the first source interconnect line is not placed over the plug.

16. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of unit MISFET elements formed in a first MISFET formation region of a main surface of the semiconductor substrate and coupled in parallel to each other;

an interconnect line structure formed over the semiconductor substrate and having a first interconnect line layer, and a second interconnect line layer located over the first interconnect line layer; and

a back surface electrode formed over a back surface of the semiconductor substrate opposite to the main surface,

wherein each of the unit MISFET elements has a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate located between the source region and the drain region via a gate insulating film,

wherein the first interconnect line layer of the interconnect line structure includes a first drain interconnect line, and a first gate interconnect line,

wherein the second interconnect line layer of the interconnect line structure includes a second drain interconnect line, and a second gate interconnect line,

wherein each of the first drain interconnect line and the first gate interconnect line has a thickness smaller than a thickness of each of the second drain interconnect line and the second gate interconnect line,

wherein the respective source regions of the unit MISFET elements are electrically coupled to the back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate to be electrically coupled to each other,

wherein the respective drain regions of the unit MISFET elements are electrically coupled to each other via the first drain interconnect line and the second drain interconnect line,

wherein the respective gate electrodes of the unit MISFET elements are electrically coupled to each other via the first gate interconnect line and electrically coupled to the second gate interconnect line via the first gate interconnect line, and

wherein the first gate interconnect line extends over the plug.

17. The semiconductor device according to claim 16,

wherein, over the first MISFET formation region, the first gate interconnect line integrally includes a portion extending in a first direction as an extending direction of each of the gate electrodes, and a portion extending in a second direction crossing the first direction, and

wherein the portion of the first gate interconnect line extending in the first direction extends over the plug in the first direction.

18. The semiconductor device according to claim 17,

wherein the first drain interconnect line is divided into a plurality of discrete drain interconnect lines with the first gate interconnect line being interposed therebetween,

wherein, over the respective drain regions of the unit MISFET elements, the discrete drain interconnect lines are placed,

wherein the second drain interconnect line is placed so as to cover the discrete drain interconnect lines, and

wherein the discrete drain interconnect lines are electrically coupled to each other via the second drain interconnect line.

19. The semiconductor device according to claim 18,

wherein, in plan view, each of the discrete drain interconnect lines is surrounded by the first gate interconnect line.

20. The semiconductor device according to claim 16,

wherein the second drain interconnect line forms a drain pad, and

wherein the second gate interconnect line forms a gate pad.