Semiconductor device
First Claim
1. A semiconductor device comprising:
- a substrate;
a gate electrode layer on the substrate;
a silicon nitride layer on the gate electrode layer;
a first silicon oxide layer on the silicon nitride layer;
an oxide semiconductor layer on and in contact with the first silicon oxide layer;
a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer;
a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layera third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer;
a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and
a pixel electrode layer on the planarizing insulating layer and overlapping the channel formation region,wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and overlapping with the gate electrode layer, andwherein the pixel electrode layer is on and in contact with the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer.
1 Assignment
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Accused Products
Abstract
An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
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Citations
34 Claims
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1. A semiconductor device comprising:
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a substrate; a gate electrode layer on the substrate; a silicon nitride layer on the gate electrode layer; a first silicon oxide layer on the silicon nitride layer; an oxide semiconductor layer on and in contact with the first silicon oxide layer; a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer; a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layer a third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer; a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and a pixel electrode layer on the planarizing insulating layer and overlapping the channel formation region, wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and overlapping with the gate electrode layer, and wherein the pixel electrode layer is on and in contact with the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
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a substrate; a gate electrode layer on the substrate; a silicon nitride layer on and in contact with the gate electrode layer; a first silicon oxide layer on and in contact with the silicon nitride layer; an oxide semiconductor layer on and in contact with the first silicon oxide layer; a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer; a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layer a third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer; a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and a pixel electrode layer on and in contact with the planarizing insulating layer and overlapping the channel formation region, wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and overlapping with the gate electrode layer, and wherein the pixel electrode layer is on and in contact with the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a substrate; a gate electrode layer on the substrate; a silicon nitride layer on the gate electrode layer; a first silicon oxide layer on the silicon nitride layer; an oxide semiconductor layer on and in contact with the first silicon oxide layer; a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer; a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layer a third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer; a third conductive layer overlapping the oxide semiconductor layer with the second silicon oxide layer and the third silicon oxide layer interposed therebetween; a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and a pixel electrode layer on the planarizing insulating layer, wherein the oxide semiconductor layer entirely overlaps with the gate electrode layer; wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and entirely overlapping with the gate electrode layer, and wherein the pixel electrode layer is electrically connected to the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A semiconductor device comprising:
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a substrate; a gate electrode layer on the substrate; a silicon nitride layer on and in contact with the gate electrode layer; a first silicon oxide layer on and in contact with the silicon nitride layer; an oxide semiconductor layer on and in contact with the first silicon oxide layer; a second silicon oxide layer on and in contact with a channel formation region of the oxide semiconductor layer and covering lateral end portions of the oxide semiconductor layer; a first conductive layer and a second conductive layer each on and in contact with the second silicon oxide layer a third silicon oxide layer on and in contact with the first conductive layer, the second conductive layer and the second silicon oxide layer; a third conductive layer overlapping the oxide semiconductor layer with the second silicon oxide layer and the third silicon oxide layer interposed therebetween; a planarizing insulating layer on the third silicon oxide layer, the planarizing insulating layer comprising an organic material; and a pixel electrode layer on and in contact with the planarizing insulating layer, wherein the oxide semiconductor layer entirely overlaps with the gate electrode layer; wherein each of the first conductive layer and the second conductive layer are on and in contact with the oxide semiconductor layer through an opening formed in the second silicon oxide layer and entirely overlapping with the gate electrode layer, and wherein the pixel electrode layer is electrically connected to the first conductive layer through an opening formed in the planarizing insulating layer and the third silicon oxide layer. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification