Thin film transistor substrate and method for producing same

• US 9,142,573 B1
• Filed: 02/14/2011
• Issued: 09/22/2015
• Est. Priority Date: 05/24/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamashita, Tetsuya, Yoshida, Tokuo, Chikama, Yoshimasa, Ohta, Yoshifumi, Mizuno, Yuuji, Suzuki, Masahiko, Nakagawa, Okifumi, Harumoto, Yoshiyuki, Miyamoto, Yoshinobu
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US13/699,377
• Publication Number:
  US 20150287742A1
• Time in Patent Office: 1,681 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.

Claims

1. A method for manufacturing a thin film transistor substrate including a plurality of pixel electrodes arranged in a matrix pattern, a plurality of thin film transistors respectively provided for the pixels electrodes and respectively connected to the pixel electrodes, and a plurality of auxiliary capacitors respectively provided for the pixel electrodes, wherein each of the thin film transistors includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, a semiconductor layer comprised of an oxide semiconductor and having a channel region provided on the gate insulating film so as to overlap the gate electrode, and a source electrode and a drain electrode which are provided on the semiconductor layer so as to be separated from each other with the channel region interposed therebetween, each of the auxiliary capacitors includes a capacitor line comprised of a same material as the gate electrode and provided in a same layer as the gate electrode, the gate insulating film provided so as to cover the capacitor line, a capacitor intermediate layer provided using the oxide semiconductor and provided on the gate insulating film so as to overlap the capacitor line, and a capacitor electrode provided on the capacitor intermediate layer, the method comprising:

a first step of forming the gate electrode and the capacitor line on the substrate;

a second step of sequentially forming the gate insulating film, an oxide semiconductor film, and a source metal film so as to cover the gate electrode and the capacitor line, then forming on the source metal film a resist pattern in which a portion corresponding to the source electrode and the drain electrode is relatively thick and a portion corresponding to the channel region and the capacitor intermediate layer is relatively thin, and subsequently, etching the source metal film exposed from the resist pattern and the oxide semiconductor film, and then thinning the resist pattern to remove the relatively thin portion, and etching the source metal film thus exposed, thereby forming the semiconductor layer, the source electrode and the drain electrode, and another semiconductor layer that serves as the capacitor intermediate layer;

a third step of forming an interlayer insulating film so as to overlap the channel region of the semiconductor layer and to expose a part of the drain electrode and the another semiconductor layer, and then making the another semiconductor layer exposed from the interlayer insulating film conductive by vacuum annealing, thereby forming the capacitor intermediate layer; and

a fourth step of forming on the interlayer insulating film the pixel electrode that functions as the capacitor electrode.

2. The method of claim 1, wherein

the oxide semiconductor is an In—

Ga—

Zn—

O oxide semiconductor layer.

3. The method of claim 1, wherein

in the second step, a silicon nitride film and a silicon oxide film are sequentially formed to cover the gate electrode and the capacitor line, thereby forming the gate insulating film.

4. The method of claim 1, wherein

in the second step, the oxide semiconductor film is formed by a sputtering method or a coating method.

5. The method of claim 1, wherein

in the second step, a titanium film and an aluminum film, a titanium film and a copper film, or a titanium film, an aluminum film, and a titanium film are sequentially formed to cover the oxide semiconductor, thereby forming the metal film.

6. The method of claim 1, wherein

the interlayer insulating film is a silicon oxide film.