Liquid crystal display device

• US 9,142,632 B2
• Filed: 03/26/2014
• Issued: 09/22/2015
• Est. Priority Date: 07/20/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): KIANNI, KAVEH C
• Application Number:
  US14/225,469
• Publication Number:
  US 20140204304A1
• Time in Patent Office: 545 Days
• Field of Search: 349/42, 349/43
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a liquid crystal display device including a thin film transistor with high electric characteristics and high reliability. As for a liquid crystal display device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, and a channel protective layer which is formed over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film.

Claims

1. A semiconductor device comprising:

a substrate;

a gate wiring over the substrate;

a first wiring over the substrate;

a second wiring and a third wiring over the substrate;

a first transistor comprising a first channel formation region, the gate wiring, a first source electrode, and a first drain electrode;

a second transistor comprising a second channel formation region, the gate wiring, a second source electrode, and a second drain electrode;

a first capacitor, one terminal of the first capacitor electrically connected to the second wiring;

a second capacitor, one terminal of the second capacitor electrically connected to the third wiring;

an insulating film over the first transistor, the second transistor, the first capacitor and the second capacitor, the insulating film including a first contact hole and a second contact hole; and

a first sub pixel electrode and a second sub pixel electrode adjacent to the first sub pixel electrode, each of the first sub pixel electrode and the second sub pixel electrode including a slit,

wherein one of the first source electrode and the first drain electrode is electrically connected to the first wiring,

wherein one of the second source electrode and the second drain electrode is electrically connected to the first wiring,

wherein the other of the first source electrode and the first drain electrode is electrically connected to the first sub pixel electrode through the first contact hole,

wherein the other of the first source electrode and the first drain electrode is electrically connected to the other terminal of the first capacitor,

wherein the other of the second source electrode and the second drain electrode is electrically connected to the second sub pixel electrode through the second contact hole,

wherein the other of the second source electrode and the second drain electrode is electrically connected to the other terminal of the second capacitor,

wherein an entire portion of a semiconductor film including the first channel formation region overlaps with the gate wiring,

wherein the first sub pixel electrode including the slit overlaps an entire portion of the first contact hole,

wherein the second sub pixel electrode including the slit overlaps an entire portion of the second contact hole, and

wherein the semiconductor film including the first channel formation region comprises silicon.

2. The semiconductor device according to claim 1, wherein the semiconductor film including the first channel formation region is a microcrystalline semiconductor film.

3. The semiconductor device according to claim 1, wherein an entire portion of a semiconductor film including the second channel formation region overlaps with the gate wiring.

4. The semiconductor device according to claim 1,

wherein the first contact hole is positioned between the gate wiring and the second wiring, and

wherein the second contact hole is positioned between the gate wiring and the third wiring.

5. The semiconductor device according to claim 1, wherein the first sub pixel electrode overlaps the semiconductor film including the first channel formation region.

6. The semiconductor device according to claim 1, wherein a shape of the slit is Y-shape.

7. The semiconductor device according to claim 1, further comprising:

a source region and a drain region over the semiconductor film.

8. The semiconductor device according to claim 1, wherein the semiconductor film including the first channel formation region comprises an amorphous portion and a crystalline portion.

9. One of a liquid crystal display device, a liquid crystal panel, and a liquid crystal display module comprising the semiconductor device according to claim 1.

10. A semiconductor device comprising:

a substrate;

a gate wiring over the substrate;

a first wiring over the substrate;

a second wiring and a third wiring over the substrate;

a first transistor comprising a first channel formation region, the gate wiring, a first source electrode, and a first drain electrode;

a second transistor comprising a second channel formation region, the gate wiring, a second source electrode, and a second drain electrode;

a first capacitor, one terminal of the first capacitor electrically connected to the second wiring;

a second capacitor, one terminal of the second capacitor electrically connected to the third wiring;

an insulating film over the first transistor, the second transistor, the first capacitor and the second capacitor, the insulating film including a first contact hole and a second contact hole; and

a first sub pixel electrode and a second sub pixel electrode adjacent to the first sub pixel electrode, each of the first sub pixel electrode and the second sub pixel electrode including a slit,

wherein one of the first source electrode and the first drain electrode is electrically connected to the first wiring,

wherein one of the second source electrode and the second drain electrode is electrically connected to the first wiring,

wherein the other of the first source electrode and the first drain electrode is electrically connected to the first sub pixel electrode through the first contact hole,

wherein the other of the first source electrode and the first drain electrode is electrically connected to the other terminal of the first capacitor,

wherein the other of the second source electrode and the second drain electrode is electrically connected to the second sub pixel electrode through the second contact hole,

wherein the other of the second source electrode and the second drain electrode is electrically connected to the other terminal of the second capacitor,

wherein an entire portion of a semiconductor film including the first channel formation region overlaps with the gate wiring,

wherein the first sub pixel electrode including the slit overlaps an entire portion of the first contact hole,

wherein the second sub pixel electrode including the slit overlaps an entire portion of the second contact hole,

wherein the second sub pixel electrode overlaps the gate wiring and the third wiring, and

wherein the semiconductor film including the first channel formation region comprises silicon.

11. The semiconductor device according to claim 10, wherein the semiconductor film including the first channel formation region is a microcrystalline semiconductor film.

12. The semiconductor device according to claim 10, wherein an entire portion of a semiconductor film including the second channel formation region overlaps with the gate wiring.

13. The semiconductor device according to claim 10,

wherein the first contact hole is positioned between the gate wiring and the second wiring, and

wherein the second contact hole is positioned between the gate wiring and the third wiring.

14. The semiconductor device according to claim 10, wherein the first sub pixel electrode overlaps the semiconductor film including the first channel formation region.

15. The semiconductor device according to claim 10, wherein a shape of the slit is Y-shape.

16. The semiconductor device according to claim 10, further comprising:

a source region and a drain region over the semiconductor film.

17. The semiconductor device according to claim 10, wherein the semiconductor film including the first channel formation region comprises an amorphous portion and a crystalline portion.

18. The semiconductor device according to claim 10, wherein the first sub pixel electrode overlaps the gate wiring and the second wiring.

19. One of a liquid crystal display device, a liquid crystal panel, and a liquid crystal display module comprising the semiconductor device according to claim 10.