Semiconductor device

• US 9,142,655 B2
• Filed: 03/12/2013
• Issued: 09/22/2015
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Cotorogea, Maria, Wolter, Frank, Schulze, Hans-Joachim, Niedernostheide, Franz-Josef, Gawlina-Schmidl, Yvonne
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/796,287
• Publication Number:
  US 20140264432A1
• Time in Patent Office: 924 Days
• Field of Search: 257/139, 257/328, 257/330, 257/E27.091, 257331-334, 257/329, 257/E21.41, 438/259, 438/270, 438/271, 438/589
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.

Claims

1. A semiconductor device in a semiconductor substrate including a first main surface, including a transistor cell, comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type between the drift region and the first main surface;

an active trench at the first main surface extending into the drift region;

a gate conductive layer in the active trench;

a source region of the first conductivity type in the body region adjacent to the active trench;

at least a first body trench and a second body trench at the first main surface extending into the drift region, the first and second body trenches being adjacent to the body region and to the drift region;

further source regions of the first conductivity type in the body region adjacent to at least one of the first and the second body trenches, at least one of the further source regions being disconnected from a source terminal;

an insulating layer at sidewalls and at a bottom side of each of the first and second body trenches; and

a conductive layer in each of the first and second body trenches,

wherein at least one of the first and second body trenches is different from the active trench.

2. The semiconductor device of claim 1, wherein a gate insulating layer is disposed in the active trench, the gate insulating layer having a thickness different from the thickness of the insulating layer of any of the first and second body trenches.

3. The semiconductor device of claim 2, wherein the thickness of the insulating layer of the first body trench is equal to the thickness of the insulating layer of the second body trench, and the thickness of the gate insulating layer is different from the thickness of the insulating layer of the first and second body trenches.

4. The semiconductor device according to claim 1, wherein

the gate conductive layer is connected with a gate terminal, and

a conductive filling is disposed in at least one of the first and second body trenches, the conductive filling of at least one of the first and second body trenches connected with the gate terminal, the at least one of the first and second body trenches being disposed adjacent to the further source regions.

5. The semiconductor device according to claim 4, wherein a conductive filling is disposed in at least one of the first and second body trenches, the conductive filling of at least one of the first and second body trenches connected with the source terminal.

6. The semiconductor device according to claim 4, wherein the body trench having the conductive filling connected with the gate terminal extends to a deeper depth than the other body trench.

10. The semiconductor device of claim 1, wherein the first and the second body trenches are disposed adjacent to each other.

7. A semiconductor device in a semiconductor substrate including a first main surface including a transistor cell, comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type, between the drift region and the first main surface;

an active trench at the first main surface extending into the drift region, a gate conductive layer being disposed in the active trench;

a source region of the first conductivity type in the body region adjacent to the active trench;

at least a first body trench and a second body trench at the first main surface extending into the drift region, the first and second body trenches being adjacent to the body region and to the drift region;

an insulating layer at sidewalls and at a bottom side of each of the first and second body trenches; and

a conductive layer in each of the first and second body trenches,

and further source regions of the first conductivity type adjacent to at least one of the first and second body trenches, at least one of the further source regions being disconnected from a source terminal,

wherein the first and the second body trenches are different from each other.

8. The semiconductor device according to claim 7, wherein a thickness of the insulating layer in the first body trench is different from a thickness of the insulating layer in the second body trench.

9. The semiconductor device according to claim 7, wherein the gate conductive layer of the active trench is connected to a gate terminal,

a conductive filling disposed in the first and the second body trenches, the conductive filling of the first body trench being connected to a source terminal, the conductive filling of the second body trench being connected to the gate terminal.

11. The semiconductor device of claim 7, wherein the first and the second body trenches are disposed adjacent to each other.

12. A semiconductor device in a semiconductor substrate including a first main surface, including a transistor cell, comprising:

a drift region of a first conductivity type;

a body region of a second conductivity type between the drift region and the first main surface;

an active trench at the first main surface extending into the drift region;

a gate conductive layer in the active trench, the gate conductive layer being connected with a gate terminal;

a source region of the first conductivity type in the body region adjacent to the active trench;

at least a first body trench and a second body trench at the first main surface extending into the drift region, the first and second body trenches being adjacent to the body region and to the drift region;

further source regions of the first conductivity type in the body region adjacent to at least one of the first and the second body trenches, at least one of the further source regions being disconnected from a source terminal;

an insulating layer at sidewalls and at a bottom side of each of the first and second body trenches; and

a conductive layer in each of the first and second body trenches,

wherein the conductive layer of at least one of the first and second body trenches connected with the gate terminal; and

the at least one of the first and second body trenches being disposed adjacent to the further source regions.

13. The semiconductor device of claim 12, wherein a gate insulating layer is disposed in the active trench, the gate insulating layer having a thickness different from the thickness of the insulating layer of any of the first and second body trenches.