Field effect transistor devices with low source resistance

• US 9,142,662 B2
• Filed: 05/16/2011
• Issued: 09/22/2015
• Est. Priority Date: 05/06/2011
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ryu, Sei-Hyung, Capell, Doyle Craig, Cheng, Lin, Dhar, Sarit, Jonas, Charlotte, Agarwal, Anant, Palmour, John
• Primary Examiner(s): Jung, Michael
• Application Number:
  US13/108,440
• Publication Number:
  US 20120280270A1
• Time in Patent Office: 1,590 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

Claims

1. A semiconductor device comprising:

a channel region extending in a first direction;

a lateral source region adjacent and parallel to the channel region;

a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; and

a source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions;

wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; and

wherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,

wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.

2. The semiconductor device of claim 1, wherein a minimum dimension of an area of contact of the source ohmic contact on the plurality of source contact regions is such that the semiconductor device has a reverse blocking voltage of 1000 volts or more and the device is capable of a forward current greater than 100 A at a forward voltage of 5 volts or less.

3. The semiconductor device of claim 1, wherein the semiconductor device comprises a metal-oxide semiconductor field effect transistor device having a reverse blocking voltage of 1200 volts or more.

4. The semiconductor device of claim 1, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the semiconductor device has a blocking voltage less than 1000 V and is configured to pass forward current at a current density greater than 200 amps per square centimeter at a forward voltage drop of 5 V or less.

5. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a ratio of sheet resistance in ohms per square of the plurality of source contact regions to contact resistance in ohms per square area is greater than 1, wherein the square is equal in size to the square area.

6. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions to have a sheet resistance in ohms per square greater than 75% of a contact resistance hi ohms per square area such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A, wherein the square is equal in size to the square area.

7. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a sheet resistance in ohms per square of the plurality of source contact regions is greater than a contact resistance in ohms per square area of the plurality of source contact regions, wherein the square is equal in size to the square area.

8. The semiconductor device of claim 1, wherein the plurality of source contact regions is arranged in the layout with the source ohmic contact and the first and second contact regions such that a sheet resistance in ohms per square of the plurality of source contact regions is at least 5 times greater than a contact resistance in ohms per square area of the plurality of source contact regions, wherein the square is equal in size to the square area.

9. The semiconductor device of claim 1, wherein the plurality of source contact regions has a sheet resistance and the source ohmic contact has a contact resistance, wherein the contact resistance in ohms per square area is greater than the sheet resistance in ohms per area, wherein the square is equal in size to the square area.

10. The semiconductor device of claim 1, further comprising a source region including the lateral source region and the source contact regions, wherein the source region is arranged in the layout to surround the first and second body contact regions.

11. The semiconductor device of claim 10, wherein the source region is arranged in the layout to surround the first and second body contact regions at a same level as the plurality of contact regions.

12. The semiconductor device of claim 1, wherein a cell pitch of the semiconductor device is less than 10 μ

m.

13. The semiconductor device of claim 1, wherein the layout comprises a number of source contact regions contacting the source ohmic contact that is one greater than a number of contact regions contacting the source ohmic contact.

14. The semiconductor device of claim 1, wherein the number of source contact regions contacting the source ohmic contact is three and the number of contact regions contacting the source ohmic contact is two.

15. The semiconductor device of claim 1, wherein a minimum dimension of an area of contact between the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A.

16. The semiconductor device of claim 1, wherein the plurality of contact regions are arranged in the layout with the plurality of source contact regions such that the first and second body contact regions are not physically contacting each other.

17. The semiconductor device of claim 1, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in a layout such that the semiconductor device has a reverse blocking voltage in excess of 1000 volts and a current density greater than 200 amps per square centimeter at a current greater than 100 A.

18. A semiconductor device comprising:

a channel region extending in a first direction;

a lateral source region adjacent and parallel to the channel region;

a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; and

a source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions;

wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; and

wherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,

wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.

19. A semiconductor device comprising:

a channel region extending in a first direction;

a lateral source region adjacent and parallel to the channel region;

a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; and

a source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions;

wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; and

wherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,

wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.

20. The insulated gate bipolar transistor device of claim 19, wherein a minimum dimension of an area of the source ohmic contact on the plurality of source contact regions is arranged in the layout such that the insulated gate bipolar transistor device has a blocking voltage of 13 kV or more and the insulated gate bipolar transistor device is capable of a forward current of 5 A or greater.

21. The insulated gate bipolar transistor device of claim 19, wherein the insulated gate bipolar transistor device has a specific on-resistance of less than 14 mOhm-cm².

22. The insulated gate bipolar transistor device of claim 21, wherein the insulated gate bipolar transistor device has a voltage blocking capability of 10 kV or more.

23. A semiconductor device comprising:

a channel region extending in a first direction;

a lateral source region adjacent and parallel to the channel region;

a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; and

a source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions;

wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; and

wherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,

wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.

24. The metal-oxide semiconductor field effect transistor device of claim 23, wherein the cell pitch is less than 10 μ

m.

25. A semiconductor device comprising:

a channel region extending in a first direction;

a lateral source region adjacent and parallel to the channel region;

a plurality of source contact regions of a first conductivity type laterally adjacent to and arranged in a layout with first and second contact regions, the first and second contact regions having a second conductivity type; and

a source ohmic contact that extends in the first direction across the plurality of source contact regions and the first and second contact regions;

wherein the source ohmic contact directly contacts each source contact region and each of the first and second contact regions of the layout; and

wherein the plurality of source contact regions and the first and second contact regions extend in a second direction perpendicular to the first direction, the plurality of source contact regions are in electrical contact with the lateral source region, and the source ohmic contact is spaced apart from the lateral source region in the second direction,

wherein the channel region and the lateral source region comprises a wide bandgap semiconductor material having a bandgap greater than about 2.0 V.