Semiconductor device and method for manufacturing the same
First Claim
1. A method for manufacturing a semiconductor device, comprising the steps of:
- forming a semiconductor layer including a source region and a drain region;
forming a gate insulating layer over the semiconductor layer;
forming a gate electrode over the gate insulating layer;
forming a pair of electrodes electrically connected to the source region and the drain region of the semiconductor layer;
forming an insulating layer over the gate electrode;
forming a first metal oxide layer having an amorphous structure over the insulating layer; and
forming a second metal oxide layer having a polycrystalline structure over the first metal oxide layer,wherein the first metal oxide layer and the second metal oxide layer are formed so as to cover the pair of electrodes.
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Accused Products
Abstract
A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor.
130 Citations
18 Claims
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1. A method for manufacturing a semiconductor device, comprising the steps of:
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forming a semiconductor layer including a source region and a drain region; forming a gate insulating layer over the semiconductor layer; forming a gate electrode over the gate insulating layer; forming a pair of electrodes electrically connected to the source region and the drain region of the semiconductor layer; forming an insulating layer over the gate electrode; forming a first metal oxide layer having an amorphous structure over the insulating layer; and forming a second metal oxide layer having a polycrystalline structure over the first metal oxide layer, wherein the first metal oxide layer and the second metal oxide layer are formed so as to cover the pair of electrodes. - View Dependent Claims (2, 3, 4, 5, 11)
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6. A method for manufacturing a semiconductor device, comprising the steps of:
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forming a semiconductor layer including a source region and a drain region; forming a gate insulating layer over the semiconductor layer; forming a gate electrode over the gate insulating layer; forming a pair of electrodes electrically connected to the source region and the drain region of the semiconductor layer; forming a first metal oxide layer having an amorphous structure over the gate electrode; forming a second metal oxide layer having a polycrystalline structure over the first metal oxide layer; and forming an insulating layer over the second metal oxide layer, wherein the first metal oxide layer and the second metal oxide layer are formed so as to cover the pair of electrodes. - View Dependent Claims (7, 8, 9, 10, 12)
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13. A method for manufacturing a semiconductor device, comprising the steps of:
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forming a semiconductor layer including a source region and a drain region; forming a gate insulating layer over the semiconductor layer; forming a gate electrode over the gate insulating layer; forming a pair of electrodes electrically connected to the source region and the drain region of the semiconductor layer; forming a first metal oxide layer over the pair of electrodes; and forming a second metal oxide layer over the first metal oxide layer, wherein the second metal oxide layer has a higher crystallinity than the first metal oxide layer, and wherein the first metal oxide layer and the second metal oxide layer are formed so as to cover the pair of electrodes. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification
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- Resources
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsWatanabe, Masahiro, Mashiyama, Mitsuo, Handa, Takuya, Okazaki, Kenichi
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Primary Examiner(s)Malsawma, Lex
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Assistant Examiner(s)LE, LONG HUYNH
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Application NumberUS13/623,913Publication NumberTime in Patent Office1,096 DaysField of Search257/57US Class Current1/1CPC Class CodesH01L 23/564 Details not otherwise provi...H01L 29/78606 with supplementary region o...H01L 29/7869 having a semiconductor body...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
