Semiconductor wafer comprising gallium nitride layer having one or more silicon nitride interlayer therein

• US 9,142,723 B2
• Filed: 10/12/2011
• Issued: 09/22/2015
• Est. Priority Date: 11/15/2010
• Status: Active Grant

• Current Assignee: Intellec Limited
• Original Assignee: Intellec Limited
• Inventors: Humphreys, Colin, McAleese, Clifford, Kappers, Menno, Liu, Zhenyu, Zhu, Dandan
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US13/885,346
• Publication Number:
  US 20130270575A1
• Time in Patent Office: 1,441 Days
• Field of Search: 257 12- 14, 257/18, 257/20
• US Class Current: 1/1
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/03048 comprising a nitride compounds, e.g. InGaN
• CPC Class Codes: H01L 31/035236 Superlattices; Multiple quantum well structures
• CPC Class Codes: H01L 31/075 the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: H01L 31/1856 comprising nitride compounds, e.g. GaN
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.

Claims

1. A semiconductor wafer havinq a diameter of at least 6 inches, comprising:

a substrate layer consisting of silicon and unavoidable impurities;

a first GaN layer having one or more SiN_x interlayers therein;

an AlGaN layer between the substrate layer and the first GaN layer; and

an AlN layer between the substrate layer and the AlGaN layer;

wherein the AlGaN layer is compositionally graded so that the amount of aluminum decreases across the thickness of the layer away from the silicon substrate layer; and

wherein in the first GaN layer at least one SiN_x interlayer has GaN penetrated through one or more portions of said SiN_x interlayer and has a thickness of from 0.5 to 10 nm.

2. The semiconductor wafer according to claim 1, comprising two or more AlGaN layers between the substrate layer and the first GaN layer, wherein each layer has the formula Al_xGa_1-xN and the value of x in each layer is from 0.01 to 0.9.

3. The semiconductor wafer according to claim 1, wherein the first GaN layer is not intentionally doped.

4. A semiconductor wafer according to claim 1, wherein the first GaN layer has two or more SiN_x interlayers therein.

5. A semiconductor wafer according to claim 1, wherein GaN penetrates through one or more portions of at least one SiN_x interlayer to form discrete crystalline structures within the GaN enclosing the SiN_x interlayer.

6. A semiconductor wafer according to claim 1, wherein the GaN penetrates through a plurality of portions of said SiN_x interlayer across said interlayer.

7. The semiconductor wafer according to claim 1, further comprising a second GaN layer on the first GaN layer, wherein the second GaN layer is intentionally doped.

8. The semiconductor wafer according to claim 7, wherein the second GaN layer is n-doped, preferably with silicon or germanium.

9. The semiconductor wafer according to claim 7, wherein the second GaN layer is a compositionally graded Si- or Ge-doped GaN layer formed on the first GaN layer so that the amount of Si or Ge respectively increases across the thickness of the layer away from the GaN layer.

10. The semiconductor wafer according to claim 7, further comprising a p-doped semiconductor layer formed on the second GaN layer.

11. The semiconductor wafer of claim 10, further comprising a layer of multiple quantum wells (MQWs) formed between the second GaN layer and the p-doped semiconductor layer, and wherein the thickness of the layer of MQWs is preferably from 10 to 200 nm.

12. The semiconductor wafer of claim 1 wherein:

the thickness of the substrate is from 275 to 1000 μ

m; and

/or

the thickness of the AlN layer, where present, is from 10-300 nm; and

/or

the thickness of the AlGaN layer, where present, is from 100 to 1500 nm; and

/or

the thickness of the first GaN layer is from 0.1 to 5 μ

m; and

/or

the thickness of each SiNx interlayer is from 0.5 to 10 nm.

13. The semiconductor wafer of claim 1 incorporated into an LED or a Solar Cell.

14. A semiconductor device comprising a semiconductor wafer as defined in claim 1.

15. A process for forming a composite wafer according to claim 1, wherein the layers are sequentially formed on the substrate using metalorganic vapour phase epitaxy (MOVPE) growth procedure.

16. The process according to claim 15, wherein after the formation of one of said SiN_x interlayers, GaN is deposited to penetrate through one or more portions of said SiNx interlayer.

17. The process according to claim 16, wherein the GaN deposited to penetrate through one or more portions of said SiNx interlayer is deposited at a temperature of from 900 to 1050°

C. and a V/III ratio of less than 1000;

1.

18. The process according to claim 16, wherein at least two or more of the layers are deposited in a single MOVPE process carried out in a single MOVPE chamber.