Fully capacitive coupled input choppers

• US 9,143,092 B2
• Filed: 12/14/2011
• Issued: 09/22/2015
• Est. Priority Date: 12/14/2011
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Huijsing, Johan Hendrik, Fan, Qinwen, Makinwa, Kofi Afolabi Anthony
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O TOOLE, COLLEEN J
• Application Number:
  US13/325,847
• Publication Number:
  US 20130154718A1
• Time in Patent Office: 1,378 Days
• Field of Search: 327/124, 327379-381, 327389-391, 327/427, 327/434, 327/436, 327/437, 330/9, 341/143
• US Class Current: 1/1
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 3/393 with field-effect devices
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 17/08104 in field-effect transistor switches H03K17/0812, H03K17/0814 take precedence
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/452 with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input

Abstract

A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Claims

1. A method of differential signal transfer from a differential input Vinp and Vinn when a common mode input voltage is higher than the power supply voltage, comprising:

providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, the first through fourth transistors being MOS transistors, and wherein the sources of the first and third transistors are coupled to the Vinp input, the sources of the second and fourth transistors are coupled to the Vinn input, the drains of the first and fourth transistors are coupled to input chopper output Voutp and the drains of the second and third transistors being coupled to the input chopper output Voutn;

providing an output chopper;

capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper;

wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage.

2. The method of claim 1 wherein the coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp or Vinn, which ever has a lower voltage, and coupling a first one replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input Vinp or Vinn, which ever is a lower voltage, reverses the voltage across the diode connected fifth transistor.

3. The method of claim 1 wherein which of the inputs Vinp or Vinn is a lower voltage is determined by providing a latch responsive the inputs Vinp and Vinn.

4. The method of claim 3 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.

5. A method of differential signal transfer from a differential input Vinp and Vinn when a common mode input voltage is higher than the power supply voltage, comprising:

providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, the first through fourth transistors being MOS transistors, and wherein the sources of the first and third transistors are coupled to the Vinp input, the sources of the second and fourth transistors are coupled to the Vinn input, the drains of the first and fourth transistors are coupled to input chopper output Voutp and the drains of the second and third transistors being coupled to the input chopper output Voutn;

providing an output chopper;

capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper;

wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to one of the inputs Vinp or Vinn.

6. The method of claim 5 wherein coupling the gates of the first and second transistors to the input Vinp or Vinn comprises capacitively coupling a diode connected fifth transistor between ground and the respective input Vinp or Vinn, and coupling a first replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input coupled to the diode connected fifth transistor reverses the voltage across the diode connected fifth transistor.

7. The method of claim 6 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.

8. The method of claim 6 further comprising:

accurately defining the start voltages of the gates of the first through fourth transistors for a next clock inversion by providing a latch having a first latch connection to the gates of the first and second transistors, and a second latch connection to the gates of the third and fourth transistors, respectively.