System and method for reducing reconfiguration power usage

• US 9,143,128 B2
• Filed: 09/15/2012
• Issued: 09/22/2015
• Est. Priority Date: 04/02/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Huang, Randy R., Voogel, Martin, Hu, Jingcao, Teig, Steven
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US13/621,124
• Publication Number:
  US 20130099821A1
• Time in Patent Office: 1,102 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17784 for supply voltage
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Claims

1. A method of generating a layout for implementing a user design on an integrated circuit (IC) that comprises reconfigurable circuits, the method comprising:

defining, at a computer, a first configuration in the layout for a reconfigurable circuit in a first reconfiguration cycle, wherein the first configuration comprises a first set of configuration values;

defining a second configuration for the reconfigurable circuit in a second reconfiguration cycle and identifying a cost for defining the second configuration;

decreasing the cost for defining the second configuration when the second configuration comprises a second set of configuration values that comprises the same values as the first set of configuration values;

based at least partly on the decreased cost, defining the second configuration for the reconfigurable circuit in the second reconfiguration cycle; and

defining a gating configuration value for blocking a reconfiguration of the reconfigurable circuit from the first reconfiguration cycle to the second reconfiguration cycle.

2. The method of claim 1 further comprising:

increasing a cost for defining a third configuration for the reconfigurable circuit in the second reconfiguration cycle, wherein the third configuration comprises a third set of configuration values that comprises a different set of values from the first set of configuration values; and

based at least partly on the increased cost, rejecting a placement of the third configuration for the reconfigurable circuit in the second reconfiguration cycle.

3. The method of claim 1 further comprising:

identifying a group of reconfigurable circuits in the layout that do not change configurations from the first reconfiguration cycle to the second reconfiguration cycle; and

defining a set of gating configuration values in the layout to block a reconfiguration of the group of circuits between the first reconfiguration cycle and the second reconfiguration cycle.

4. The method of claim 3, wherein the group of reconfigurable circuits comprises at least one reconfigurable circuit that has a “

don'"'"'t care”

configuration in a particular reconfiguration cycle.

5. The method of claim 4 further comprising defining a configuration for the reconfigurable circuit in the particular reconfiguration cycle, wherein the defined configuration (i) matches a configuration in an adjacent reconfiguration cycle and (ii) does not implement an operation of the user design.

6. A method of defining a layout of an integrated circuit (“

IC”

) with a plurality of groups of reconfigurable circuits, the method comprising;

identifying, at a computer, a first cost for a first set of configurations in a plurality of reconfiguration cycles for a group of reconfigurable circuits in the layout, wherein configuration values of the first set of configurations do not change from a first reconfiguration cycle to a second reconfiguration cycle;

identifying, at the computer, a second cost for a second set of configurations in the plurality of reconfiguration cycles for the group of reconfigurable circuits in the layout, wherein configuration values of the second set of configurations do change from the first reconfiguration cycle to the second reconfiguration cycle; and

based on the first and second costs, selecting one configuration from the first and second configurations for configuring the group of reconfigurable circuits.

7. The method of claim 6, wherein a configuration for a gating circuit associated with the group comprises a third set of configuration values, wherein each configuration value in the third set of configuration values determines whether the gating circuit will prevent the group of reconfigurable circuits from reconfiguring in a particular reconfiguration cycle.

8. The method of claim 7, wherein the second reconfiguration cycle immediately follows the first reconfiguration cycle.

9. The method of claim 8, wherein the third set of configuration values determines that the gating circuit will prevent the group of reconfigurable circuits from reconfiguring in the second reconfiguration cycle.

10. The method of claim 6, wherein the group of reconfigurable circuits share a common set of select lines.

11. The method of claim 10, wherein the common set of select lines cannot selectively reconfigure a subset of the reconfigurable circuits in the group of reconfigurable circuits without reconfiguring all of the reconfigurable circuits in the group of reconfigurable circuits.

12. A non-transitory machine readable medium storing a program for generating a layout for implementing a user design on an integrated circuit (IC) that comprises reconfigurable circuits, the program comprising sets of instructions for:

defining a first configuration, in the layout, for a reconfigurable circuit in a first reconfiguration cycle, wherein the first configuration comprises a first set of configuration values;

defining a second configuration for the reconfigurable circuit in a second reconfiguration cycle and identifying a cost for defining the second configuration;

decreasing the cost for defining the second configuration when the second configuration comprises a second set of configuration values that comprises the same values as the first set of configuration values;

based at least partly on the decreased cost, defining the second configuration for the reconfigurable circuit in the second reconfiguration cycle; and

defining a gating configuration value for blocking a reconfiguration of the reconfigurable circuit from the first reconfiguration cycle to the second reconfiguration cycle.

13. The non-transitory machine readable medium of claim 12, wherein the program further comprises sets of instructions for:

increasing a cost for defining a third configuration for the reconfigurable circuit in the second reconfiguration cycle, wherein the third configuration comprises a third set of configuration values that comprises a different set of values from the first set of configuration values; and

based at least partly on the increased cost, rejecting a placement of the third configuration for the reconfigurable circuit in the second reconfiguration cycle.

14. The non-transitory machine readable medium of claim 12, wherein the program further comprises sets of instructions for:

identifying a group of reconfigurable circuits in the layout that do not change configurations from the first reconfiguration cycle to the second reconfiguration cycle; and

defining a set of gating configuration values in the layout to block a reconfiguration of the group of circuits between the first reconfiguration cycle and the second reconfiguration cycle.

15. The non-transitory machine readable medium of claim 14, wherein the group of reconfigurable circuits comprises at least one reconfigurable circuit that has a “

don'"'"'t care”

configuration in a particular reconfiguration cycle.

16. The non-transitory machine readable medium of claim 15, wherein the program further comprises a set of instructions for defining a configuration for the reconfigurable circuit in the particular reconfiguration cycle, wherein the defined configuration (i) matches a configuration in an adjacent reconfiguration cycle and (ii) does not implement an operation of the user design.

17. A non-transitory machine readable medium storing a program for defining a layout of an integrated circuit (“

IC”

) with a plurality of groups of reconfigurable circuits, the program comprising sets of instructions for;

identifying a first cost for a first set of configurations in a plurality of reconfiguration cycles for a group of reconfigurable circuits in the layout, wherein configuration values of the first set of configurations do not change from a first reconfiguration cycle to a second reconfiguration cycle;

identifying a second cost for a second set of configurations in the plurality of reconfiguration cycles for the group of reconfigurable circuits in the layout, wherein configuration values of the second set of configurations do change from the first reconfiguration cycle to the second reconfiguration cycle; and

based on the first and second costs, selecting one configuration from the first and second configurations for configuring the group of reconfigurable circuits.

18. The non-transitory machine readable medium of claim 17, wherein a configuration for a gating circuit associated with the group comprises a third set of configuration values, wherein each configuration value in the third set of configuration values determines whether the gating circuit will prevent the group of reconfigurable circuits from reconfiguring in a particular reconfiguration cycle.

19. The non-transitory machine readable medium of claim 18, wherein the second reconfiguration cycle immediately follows the first reconfiguration cycle.

20. The non-transitory machine readable medium of claim 19, wherein the third set of configuration values determines that the gating circuit will prevent the group of reconfigurable circuits from reconfiguring in the second reconfiguration cycle.