Radio frequency multi-port switches
First Claim
1. A radio frequency (RF) switch circuit with a first port, a first enable line, a second port, a second enable line, and a common antenna port, the switch circuit comprising:
- a first transistor connected to the first port, the common antenna port, and the first enable line, the first transistor being selectively activatable in response to a first enable signal applied to the first enable line;
a second transistor connected to the second port, the common antenna port, and the second enable line, the second transistor being selectively activatable in response to a second enable signal applied to the second enable line; and
a first inductor connected across the first port to the second port to compensate for parasitic capacitance between the first port and the second port from an inactive one of the first and second transistors.
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Accused Products
Abstract
A multiport radio frequency (RF) switch circuit is disclosed. The switch circuit includes a first transistor that is connected to a first port, a common antenna port, and a first enable line. The first transistor is selectively activatable in response to a first enable signal applied to the first enable line. There is also a second transistor connected to a second port, the common antenna port, and a second enable line. The second transistor is selectively activatable in response to a second enable signal applied to the second enable line. A first inductor connected to the first port and the second port compensates for parasitic capacitance between the first port and the second port from an inactive one of the transistors.
33 Citations
30 Claims
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1. A radio frequency (RF) switch circuit with a first port, a first enable line, a second port, a second enable line, and a common antenna port, the switch circuit comprising:
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a first transistor connected to the first port, the common antenna port, and the first enable line, the first transistor being selectively activatable in response to a first enable signal applied to the first enable line; a second transistor connected to the second port, the common antenna port, and the second enable line, the second transistor being selectively activatable in response to a second enable signal applied to the second enable line; and a first inductor connected across the first port to the second port to compensate for parasitic capacitance between the first port and the second port from an inactive one of the first and second transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification