Method and system for speed negotiation for twisted pair links using intelligent E-FIFO in fibre channel systems

• US 9,143,464 B2
• Filed: 11/05/2012
• Issued: 09/22/2015
• Est. Priority Date: 12/02/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ghiasi, Ali
• Primary Examiner(s): Lee, Jae Y
• Application Number:
  US13/668,517
• Publication Number:
  US 20130058363A1
• Time in Patent Office: 1,051 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

Systems, apparatuses and methods are disclosed for using elastic buffers in fiber channel systems over twisted pair links. One such system includes a fiber channel host device and another fiber channel host device communicatively coupled to the fiber channel device over a twisted pair link. The system also includes a slave physical layer (PHY) circuit residing in the fiber channel host device and a master PHY circuit residing in the another fiber channel host device. The master PHY circuit is operable to transmit, using a reference clock, data from a transmit elastic buffer. The slave PHY circuit is operable to receive the data transmitted by the master PHY circuit and to store the received data using a derived clock recovered from the received data.

Claims

1. An apparatus residing in a fibre channel host device, the fibre channel host device communicatively coupled to another fibre channel host device over a twisted pair link, the apparatus comprising:

a physical layer (PHY) circuit operable, in a slave mode of operation, to receive data transmitted over the twisted pair link from a master PHY circuit in the another fibre channel host device, the PHY circuit comprising;

a pulse amplitude modulation (PAM) encoder/decoder operable to convert the data transmitted over the twisted pair link to PAM symbols;

clock recovery logic operable to recover a derived clock from the received data, wherein the derived clock determines a transmission rate between the PHY circuit and the master PHY circuit for the data received from the master PHY circuit; and

a first elastic buffer operable to store the data received from the master PHY circuit via the PAM encoder/decoder and a second elastic buffer operable to store data received from the fibre channel host device for outgoing transmission to the master PHY circuit over the twisted pair link via the PAM encoder/decoder, wherein the transmission rate between the PAM encoder/decoder and the first elastic buffer is the same as the transmission rate between the PAM encoder/decoder and the second elastic buffer, while the transmission rate for data being transmitted from the PHY circuit and the fibre channel host device is different than the transmission rate being transmitted from the fibre channel host device to the PHY circuit.

2. The apparatus of claim 1, wherein the first elastic buffer is further operable to use the derived clock in storing the data received from the master PHY circuit.

3. The apparatus of claim 1, the PHY circuit further comprising a pointer into the first elastic buffer that is driven by the derived clock.

4. The apparatus of claim 1, the PHY circuit further comprising:

an input pointer into the first elastic buffer that is driven by the derived clock; and

an output pointer into the first elastic buffer that is driven from a reference clock.

5. The apparatus of claim 1, wherein the PHY circuit is further operable to pass, in a manner that is synchronous with respect to a global clock, the received data to a media access control (MAC) layer which is associated with the fibre channel host device and at which decoding of the received data is performed, the global clock being different from the derived clock.

6. The apparatus of claim 5, wherein the global clock is different from the derived clock in at least one of phase and frequency.

7. The apparatus of claim 5, wherein the apparatus is operable to receive without a receive clock wire between the MAC and the PHY circuit.

8. The apparatus of claim 1, wherein the PHY circuit is further operable to determine a priority level based at least in part on an amount of data in the first elastic buffer;

and modify a contents of the first elastic buffer based at least in part on the priority level, wherein the modification occurs in response to the priority level indicating that the first elastic buffer is empty, and the modification includes at least inserting an IDLE word and at least one word from an order set comprising;

an alternate to IDLE ARB(ff), ARB(fb) for blocking ARB, ARB(src_alpha) for address assignment, no operating system (NOS), offline state (OLS), link reset (LR), link reset response (LRR), loop initialization primitive (LIP), loop port bypass (LPB), and loop port enable (LPE).

9. In a fibre channel host device communicatively coupled to another fibre channel host device over twisted pair, a method comprising:

receiving, by a physical layer (PHY) circuit, data transmitted from a master PHY circuit, the master PHY circuit residing in the another fibre channel host device;

converting, by a pulse amplitude modulation (PAM) encoder/decoder, the data transmitted over the twisted pair link to PAM symbols

recovering a derived clock from the received data, wherein the derived clock determines a transmission at which the received data is transmitted from the master PHY circuit; and

storing, in a first elastic buffer, the data received from the master PHY circuit via the PAM encoder/decoder and storing, in a second elastic buffer, data received from the fibre channel host device for outgoing transmission to the master PHY circuit over the twisted pair link via the PAM encoder/decoder, wherein the transmission rate between the PAM encoder/decoder and the first elastic buffer is the same as the transmission rate between the PAM encoder/decoder and the second elastic buffer, while the transmission rate for data being transmitted from the PHY circuit and the fibre channel host device is different than the transmission rate being transmitted from the fibre channel host device to the PHY circuit.

10. The method of claim 9, wherein a global clock is different from the derived clock in at least one of phase and frequency.

11. The method of claim 9, wherein the storing uses the derived clock.

12. The method of claim 9, further comprising:

maintaining a pointer into the first elastic buffer that is driven by the derived clock.

13. The method of claim 9, further comprising:

providing an input pointer into the first elastic buffer that is driven by the derived clock; and

providing an output pointer into the first elastic buffer that is driven from a reference clock.

14. A fibre channel system comprising:

a fibre channel host device;

another fibre channel host device communicatively coupled to the fibre channel device over a twisted pair link;

a slave physical layer (PHY) circuit residing in the fibre channel host device; and

a master PHY circuit residing in the another fibre channel host device, the master PHY circuit operable to transmit, using a reference clock, data from a transmit elastic buffer over the twisted pair link to the slave PHY circuit, and

the slave PHY circuit including;

a pulse amplitude modulation (PAM) encoder/decoder operable to convert the data transmitted over the twisted pair link to PAM symbols;

clock recovery logic operable to recover a derived clock from the received data, wherein the derived clock determines a transmission rate between the PHY circuit and the master PHY circuit for the data received from the master PHY circuit; and

a first elastic buffer operable to store the data received from the master PHY circuit via the PAM encoder/decoder and a second elastic buffer operable to store data received from the fibre channel host device for outgoing transmission to the master PHY circuit over the twisted pair link via the PAM encoder/decoder, wherein the transmission rate between the PAM encoder/decoder and the first elastic buffer is the same as the transmission rate between the PAM encoder/decoder and the second elastic buffer, while the transmission rate for data being transmitted from the PHY circuit and the fibre channel host device is different than the transmission rate being transmitted from the fibre channel host device to the PHY circuit.

15. The system of claim 14, wherein the slave PHY circuit further comprises an input pointer into the first elastic buffer, the input pointer driven by the derived clock, and wherein the master PHY circuit further comprises an output pointer into the transmit elastic buffer, the output pointer driven from the reference clock.