Shielded vertically stacked data line architecture for memory
First Claim
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1. An apparatus comprising:
- a first string of vertically stacked memory cells;
a first plurality of vertically stacked data lines, wherein a data line of the first plurality of data lines is coupled to the first string of memory cells through a first select device;
a second string of vertically stacked memory cells; and
a second plurality of vertically stacked data lines, wherein a data line of the second plurality of data lines is coupled to the second string of memory cells through a second select device and is adjacent to the data line coupled to the first string of memory cells,wherein the apparatus is configured to couple the data line coupled to the first string of memory cells to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells.
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Abstract
Apparatuses and methods include an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.
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Citations
41 Claims
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1. An apparatus comprising:
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a first string of vertically stacked memory cells; a first plurality of vertically stacked data lines, wherein a data line of the first plurality of data lines is coupled to the first string of memory cells through a first select device; a second string of vertically stacked memory cells; and a second plurality of vertically stacked data lines, wherein a data line of the second plurality of data lines is coupled to the second string of memory cells through a second select device and is adjacent to the data line coupled to the first string of memory cells, wherein the apparatus is configured to couple the data line coupled to the first string of memory cells to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. An apparatus comprising:
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a first string of vertically stacked memory cells; a second string of vertically stacked memory cells adjacent to the first string of memory cells; a third string of vertically stacked memory cells adjacent to the second string of memory cells; and a plurality of vertically stacked data lines above the first, second and third string of memory cells, wherein a first data line of the plurality of data lines is coupled to the first string of memory cells through a first select device, a second data line of the plurality of data lines is coupled to the second string of memory cells through a second select device, a third data line of the plurality of data lines is coupled to the third string of memory cells through a third select device, the second data line being above the first data line, and the third data line being above the second data line, wherein the apparatus is configured to couple the first and third data lines to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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41. An apparatus comprising:
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a plurality of vertically stacked data lines, each vertically stacked data line of the plurality of vertically stacked data lines coupled to a respective one of strings of memory cells; and a node switchably coupled to the plurality of vertically stacked data lines and configured to provide a plurality of potentials responsive to different memory operations wherein alternate ones of the plurality of vertically stacked data lines are configured to be switched to the node during a particular memory operation.
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Specification