Semiconductor memory device

• US 9,147,494 B2
• Filed: 04/14/2015
• Issued: 09/29/2015
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tokiwa, Naoya
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/686,694
• Publication Number:
  US 20150221390A1
• Time in Patent Office: 168 Days
• Field of Search: 365/185.11, 365/189.02
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Claims

1. A semiconductor memory device, comprising:

a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string;

a first bit line connected to one terminal of the first memory string and one terminal of the second memory string;

a plurality of word lines connected to the plurality of memory strings and

a controller configured to control an erase operation of the memory block, wherein the erase operation includes;

applying a first erase voltage to the plurality of word lines;

selecting the first memory string;

applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and

when the first memory string passes the erase verify, selecting the second memory string without first discharging the plurality of word lines, and

when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number.

2. The semiconductor memory device of claim 1, further comprising:

a sense amplifier connected to the first bit line,

wherein the controller is configured to apply an enable signal for the sense amplifier twice during the erase verify for the first memory string and the second memory string.

3. The semiconductor memory device of claim 2, wherein the controller is configured to carry out the erase verify for each memory string and to store results of erase verify for each memory string in a first cache.

4. The semiconductor memory device of claim 3, wherein the sense amplifier includes a logic circuit configured to determine whether a memory string passed or failed the erase verify.

5. The semiconductor memory device of claim 4, wherein the sense amplifier includes a second cache for storing the output of the logic circuit.

6. The semiconductor memory device of claim 5, further comprising a verify circuit, the verify circuit including a first register and a second register, the first register being capable of holding a first data indicating whether the erase verify for each string has passed, the second register being capable of holding a second data indicating whether an accumulated string erase verify has passed.

7. The semiconductor memory device of claim 6, further comprising an output buffer, the output buffer outputting the first data or the second data based on an instruction from outside.

8. The semiconductor memory device of claim 7, wherein the controller is configured to carryout the erase verify for each memory string based on a first signal and to carry out the accumulated string erase verify for all memory string based on a second signal, the first signal being different from the second signal.

9. The semiconductor memory device of claim 1, wherein the controller is configured to carry out the erase verify for each memory string and to store results of the erase verify for each memory string in a first cache.

10. The semiconductor memory device of claim 9, wherein the sense amplifier includes a logic circuit configured to determine whether a memory string passed or failed the erase verify.

11. The semiconductor memory device of claim 1, wherein the controller is configured to carry out an accumulated string erase verify for all memory strings, and the controller is configured to determine whether the erase verify passed or failed for all memory strings based on a result of the accumulated string erase verify.

12. The semiconductor memory device of claim 1, wherein the sense amplifier includes a logic circuit configured to determine whether a memory string passed or failed the erase verify.

13. The semiconductor memory device of claim 12, wherein the sense amplifier includes a second cache for storing the output of the logic circuit.

14. The semiconductor memory device of claim 1, further comprising a verify circuit, the verify circuit including a first register and a second register, the first register being capable of holding a first data indicating whether the erase verify for each string has passed, the second register being capable of holding a second data indicating whether an accumulated string erase verify has passed.

15. The semiconductor memory device of claim 14, further comprising an output buffer, the output buffer outputting the first data or the second data based on an instruction from outside.

16. A memory system, comprising:

a memory block including a plurality of memory strings the plurality of memory strings including a first memory string and a second memory string;

a first bit line connected to one terminal of the first memory string and one terminal of the second memory string;

a plurality of word lines connected to the plurality of memory strings;

a controller configured to control an erase operation of the memory block, wherein the erase operation includes;

applying a first erase voltage to the plurality of word lines;

selecting the first memory string;

applying an erase verify voltage to the plurality of word lines and reading data of the first memory string;

when the first memory string passes the erase verify, selecting the second memory string without first discharging the plurality of word lines; and

when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number,

wherein the controller is further configured to carry out a n accumulated string erase verify for all memory strings, and the controller is configured to determine whether the erase verify passed or failed for all memory strings based on a result of the accumulated string erase verify.

17. The memory system of claim 16, further comprising:

a sense amplifier connected to the first bit line,

wherein the controller is configured to apply an enable signal for the sense amplifier twice during the erase verify for the first memory string and the second memory string.