Semiconductor memory device
First Claim
1. A semiconductor memory device, comprising:
- a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string;
a first bit line connected to one terminal of the first memory string and one terminal of the second memory string;
a plurality of word lines connected to the plurality of memory strings anda controller configured to control an erase operation of the memory block, wherein the erase operation includes;
applying a first erase voltage to the plurality of word lines;
selecting the first memory string;
applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and
when the first memory string passes the erase verify, selecting the second memory string without first discharging the plurality of word lines, andwhen the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number.
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Accused Products
Abstract
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.
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Citations
17 Claims
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1. A semiconductor memory device, comprising:
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a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings and a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; selecting the first memory string; applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; and when the first memory string passes the erase verify, selecting the second memory string without first discharging the plurality of word lines, and when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A memory system, comprising:
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a memory block including a plurality of memory strings the plurality of memory strings including a first memory string and a second memory string; a first bit line connected to one terminal of the first memory string and one terminal of the second memory string; a plurality of word lines connected to the plurality of memory strings; a controller configured to control an erase operation of the memory block, wherein the erase operation includes; applying a first erase voltage to the plurality of word lines; selecting the first memory string; applying an erase verify voltage to the plurality of word lines and reading data of the first memory string; when the first memory string passes the erase verify, selecting the second memory string without first discharging the plurality of word lines; and when the first memory string fails the erase verify, discharging the plurality of word lines and repeating the erase operation on the memory block so long as a number of repeated erase operations performed on the memory block is less than a first number, wherein the controller is further configured to carry out a n accumulated string erase verify for all memory strings, and the controller is configured to determine whether the erase verify passed or failed for all memory strings based on a result of the accumulated string erase verify. - View Dependent Claims (17)
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Specification