Selective die electrical insulation by additive process

• US 9,147,583 B2
• Filed: 10/27/2010
• Issued: 09/29/2015
• Est. Priority Date: 10/27/2009
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Leal, Jeffrey S.
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): DEHNE, AARON A
• Application Number:
  US12/913,529
• Publication Number:
  US 20110266684A1
• Time in Patent Office: 1,798 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82051 Forming additional members
• CPC Class Codes: H01L 2224/82101 by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82355 having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

Claims

1. A method for forming an interconnected stacked die assembly, comprising:

providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge;

stacking a plurality of said die such that a die edge at the interconnect margin of a first die is offset in relation to a die edge at the interconnect margin of a second die, and a plurality of the interconnect pads of successive die in the stack are arranged in a column;

and then selectively depositing a dielectric material via a nozzle to provide electrical insulation on less than all of the interconnect pads in the column such that at least some of the interconnect pads in the column are free from being electrically insulated without requiring the deposited dielectric material to be removed and the at least some interconnect pads are available for electrical connection while other interconnect pads in the column are electrically insulated, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at a selected interconnect pad in the column and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad in the column.

2. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected region of a sidewall surface of at least one die in the stack.

3. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected area of a front side of at least one die in the stack.

4. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected area inboard of at least one of the other interconnect pads.

5. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected area of the interconnect margin of at least one die in the stack.

6. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected area adjacent the interconnect die edge of at least one die in the stack.

7. The method of claim 1 wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected area between interconnect pads.

8. The method of claim 1, further comprising forming a conformal electrically conductive trace contacting an interconnect pad and passing over an insulating region resulting from selectively depositing the dielectric material.

9. The method of claim 8 wherein the dielectric material is characterized by having a surface at least partly nonwettable by the electrically conductive material.

10. The method of claim 8, further comprising treating the deposited dielectric material so that a surface thereof is at least partly nonwettable by the electrically conductive material.

13. The method of claim 8, wherein when forming the conformal electrically conductive trace, at least a portion of a front or rear side of a die disposed at a top of the stack is substantially free from dielectric material such that semiconductor material of the die is exposed while a sidewall thereof includes the dielectric material.

14. The method of claim 1, wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected region of a sidewall surface of a top die disposed at the top of the stack such that at least a portion of a front surface of the top die remains substantially free from being deposited with the dielectric material and a semiconductor material comprising the die is substantially exposed at the front surface;

and

further comprising forming an electrically conductive trace over the dielectric material over the selected region while the dielectric material is disposed thereon and while the at least a portion of the front surface of the top die remains substantially free from the dielectric material.

16. The method of claim 2, wherein the selected region of the sidewall surface is within a trajectory defined by positions of the interconnect pads in the column, and selectively depositing the dielectric material onto the selected region covers the selected region with a discrete patch of the dielectric material.

17. The method of claim 1, further comprising:

selectively depositing the dielectric material via the nozzle onto an interconnect sidewall of at least one die in the stack during intervals when the flow axis is directed at a selected area of the interconnect sidewall.

11. A method for forming a stacked die assembly, comprising:

providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge;

stacking a plurality of said die such that the pads in successive die in the stack are arranged in a column;

and then selectively depositing electrical insulation via a nozzle on less than all of the interconnect pads in the column such that at least some of the interconnect pads in the column are free from being electrically insulated without requiring the deposited electrical insulation to be removed and the at least some interconnect pads are available for electrical connection while other interconnect pads in the column are electrically insulated, the nozzle being controlled so that the dielectric material flows from the nozzle during intervals when a flow axis of the nozzle is directed at a selected interconnect pad in the column and does not flow from the nozzle during intervals when the flow axis is directed at an unselected interconnect pad in the column; and

forming electrically conductive traces over the columns.

12. The method of claim 11, wherein the plurality of said die are in an offset configuration in which successive die in the stack are offset at the interconnect die edge.

15. The method of claim 11, wherein the selectively depositing the dielectric material also includes depositing the dielectric material onto a selected region of a sidewall surface of a top die disposed at the top of the stack such that at least a portion of a front surface of the top die remains substantially free from being deposited with the dielectric material and a semiconductor material comprising the die is exposed at the front surface;

and

forming the electrically conductive traces includes forming an electrically conductive trace over the selected region while the dielectric material is disposed thereon and while the at least a portion of the front surface of the top die remains substantially free from the dielectric material.

18. The method of claim 11, further comprising:

selectively depositing the electrical insulation via the nozzle onto an interconnect sidewall of at least one die in the stack during intervals when the flow axis is directed at a selected area of the interconnect sidewall.

19. The method of claim 18, further comprising:

positioning the flow axis in a first angular relationship with respect to a front surface of the at least one die for selectively depositing the electrical insulation on less than all of the interconnect pads in the column, and

positioning the flow axis in a second angular relationship with respect to the front surface of the at least one die for selectively depositing the electrical insulation on the interconnect sidewall of the at least one die.

20. The method of claim 19, wherein in the first angular orientation, the flow axis is perpendicular to the front surface of the at least one die, and in the second angular orientation, the flow axis is parallel to the front surface of the at least one die.