ROM chip manufacturing structures

• US 9,147,606 B2
• Filed: 07/10/2013
• Issued: 09/29/2015
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/938,776
• Publication Number:
  US 20150016173A1
• Time in Patent Office: 811 Days
• Field of Search: 365/94, 365/104
• US Class Current: 1/1
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Claims

1. An integrated circuit (IC) chip comprising:

a read-only-memory (ROM) array comprising a plurality of rows of ROM cells, wherein each row of the plurality of rows of ROM cells comprises;

a plurality of physically separated gate structures, wherein respective lengths of each of the plurality of physically separated gate structures are substantially uniform, and wherein each row of the plurality of rows runs in a direction substantially parallel to a lengthwise direction of each of the plurality of physically separated gate structures; and

a plurality of first connection modules electrically connecting each of the plurality of physically separated gate structures to a common word line.

2. The IC chip of claim 1, wherein the each of the plurality of physically separated gate structures span four, eight, sixteen, thirty-two, or sixty-four ROM cells.

3. The IC chip of claim 1, wherein the plurality of first connection modules are disposed over and contact continuous areas the plurality of gate structures.

4. The IC chip of claim 1, wherein the plurality of first connection modules are disposed over separated areas of the plurality of gate structures, wherein each of the plurality of first connection modules contact two physically separated and adjacent ones of the plurality of gate structures.

5. The IC chip of claim 1, wherein the ROM array further comprises a plurality of isolation devices disposed between the plurality of rows, and wherein gates of the plurality of isolation devices are electrically connected to ground potential.

6. The IC chip of claim 5, wherein the ROM array further comprises a second connection module electrically connecting the gates of the plurality of isolation devices to a common ground line.

7. The IC chip of claim 5, wherein gates of a first row of isolation devices of the plurality of isolation devices are physically connected together.

8. The IC chip of claim 5, wherein gates of a first row of isolation devices of the plurality of isolation devices are physically separated.

9. A method comprising:

providing a read-only-memory (ROM) array comprising a row comprising a plurality of ROM bit cells, the plurality of ROM bit cells each comprising a gate, wherein the row runs in a direction substantially parallel to a lengthwise direction of gates of the plurality of ROM bit cells; and

physically separating the gates of the plurality of ROM bit cells in the row at regular intervals.

10. The method of claim 9, further comprising electrically connecting physically separated gates of the plurality of ROM bit cells to a common word line.

11. The method of claim 10, wherein electrically connecting the physically separated gates comprises disposing a connection module on a continuous area on each of the physically separated gates.

12. The method of claim 10, wherein electrically connecting the physically separated gates comprises disposing a connection module over a first gate and a second gate of the physically separated gates, wherein the connection module is coupled to both the first gate and the second gate.

13. The method of claim 9, wherein physically separating gates of the plurality of ROM bit cells at regular intervals comprises physically separating gates of the plurality of ROM bit cells at every four, eight, sixteen, thirty-two, or sixty-four ROM bit cells.

14. A read-only-memory (ROM) array comprising:

a first row comprising a plurality of physically separated first gate structures, wherein each of the plurality of physically separated first gate structures is electrically connected to a first word line, and wherein the first row runs in a direction substantially parallel to a lengthwise direction of the plurality of physically separated first gate structures; and

a second row comprising a plurality of physically separated second gate structures, wherein each of the physically separated second gate structures is electrically connected to a second word line, wherein the second row is substantially parallel to the first row, and wherein lengths of each of the plurality of physically separated first gate structures and each of the plurality of physically separated second gate structures are substantially uniform.

15. The ROM array of claim 14 further comprising a connection module electrically connecting a first one of the plurality of physically separated first gate structures to the first word line.

16. The ROM array of claim 15, wherein the connection module is disposed on a continuous area of the first one of the plurality of physically separated first gate structures.

17. The ROM array of claim 15, wherein the connection module further electrically connects a second one of the plurality of physically separated first gate structures to the first word line.

18. The ROM array of claim 17, wherein the connection module comprises a first gate contact disposed on both the first one and the second one of the physically separated first gate structures.

19. The ROM array of claim 17, wherein the connection module comprises:

a first gate contact disposed on the first one of the physically separated first gate structures; and

a second gate contact disposed on the second one of the physically separated first gate structures.

20. The ROM array of claim 14 further comprising a third row comprising one or more third gate structures electrically connected to ground potential, wherein the third row is disposed between the first row and the second row.