Contact-based encapsulation

• US 9,147,635 B2
• Filed: 12/13/2010
• Issued: 09/29/2015
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John, Callahan, John, Dudoff, Gregory
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US12/966,699
• Publication Number:
  US 20110147932A1
• Time in Patent Office: 1,751 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13084 : Four-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1358 : being stacked
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/45111 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81054 : Composition of the atmosphere
• CPC Class Codes: H01L 2224/81136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/81825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/81894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01S 2301/176 : Specific passivation layers on surfaces other than the emission facet
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H01S 5/0422 : with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/0425 : Electrodes, e.g. characterised by the structure
• CPC Class Codes: H01S 5/04254 : characterised by the shape
• CPC Class Codes: H01S 5/04257 : having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/183 : having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/18308 : having a special structure for lateral current or light confinement

Abstract

An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

Claims

1. A method comprising:

providing a first chip comprising a first electrical contact that includes a first integrated circuit (IC) pad, a first barrier layer over the first IC pad, and a malleable material disposed over the first harrier layer that is different from the first barrier layer;

providing a second chip comprising a second electrical contact that includes a second IC pad, a rigid metal post disposed over the second IC pad, and a diffusion barrier layer disposed over the rigid metal post; and

electrically connecting the first electrical contact to the second electrical contact such that the malleable material is substantially disposed between the first barrier layer and the diffusion barrier layer and the rigid metal post is at least partially enclosed within the malleable material;

wherein the diffusion barrier layer prevents interdiffusion of the malleable material with the rigid metal post.

2. The method of claim 1, wherein said electrically connecting the first electrical contact to the second electrical contact comprises penetrating the rigid metal post into the malleable material.

3. The method of claim 2, wherein said penetrating the rigid metal post into the malleable material is performed at a temperature below a melting point of the malleable material.

4. The method of claim 1, wherein the second chip further comprises a second barrier layer over the second IC pad, and wherein the rigid metal post is located between the malleable material and one of the first or second barrier layers after said electrically connecting the first electrical contact to the second electrical contact.

5. The method of claim 4, wherein the rigid metal post and at least one of the first or second barrier layers comprise the same metal, and wherein the second barrier layer is in direct contact with both the second IC pad and the malleable material after said electrically connecting the first electrical contact to the second electrical contact.

6. The method of claim 1, wherein the second chip further comprises a non-oxidation layer disposed over the diffusion barrier layer that is different from the diffusion barrier layer.

7. The method of claim 6, wherein the non-oxidation layer comprises gold.

8. The method of claim 1, wherein the malleable material comprises a metal or alloy having a melting point of less than 1000 degrees Celsius, and wherein the rigid metal post comprises a metal or alloy having a melting temperature at least 50 degrees Celsius higher than the melting point of the malleable material.

9. The method of claim 1, wherein the first barrier layer completely covers the first IC pad.

10. The method of claim 1, wherein the diffusion barrier layer completely covers the second IC pad.

11. The method of claim 1, wherein the rigid metal post and at least one of the first barrier layer or the diffusion barrier layer comprise the same metal.

12. The method of claim 1, wherein edges of the malleable material extend beyond edges of the rigid metal post after said electrically connecting the first electrical contact to the second electrical contact.

13. The method of claim 1, wherein the malleable material is in direct contact with both the first barrier layer and the diffusion barrier layer after said electrically connecting the first electrical contact to the second electrical contact.

14. The method of claim 1, wherein the malleable material has a height of no greater than 15 microns.

15. The method of claim 1, wherein one of the first or second chips has a trench, and wherein the malleable material is substantially aligned with the trench.

16. The method of claim 1, wherein the diffusion barrier layer is in direct contact with both the rigid metal post and the malleable material after said electrically connecting the first electrical contact to the second electrical contact.

17. The method of claim 16, wherein the first barrier layer is in direct contact with both the first IC pad and the malleable material.

18. The method of claim 1, wherein the diffusion barrier layer comprises one of chromium, titanium, platinum, or palladium.

19. The method of claim 1, wherein the diffusion barrier layer comprises nickel.

20. A method comprising:

electrically connecting a first electrical contact of a first chip with a second electrical contact of a second chip;

wherein, prior to said electrically connecting, the first electrical contact includes a first integrated circuit (IC) pad, a first barrier layer over the first IC pad, and a malleable electrically-conductive material that is disposed over the first barrier layer and that is different from the first barrier layer;

wherein, prior to said electrically connecting, the second electrical contact includes a second IC pad, a rigid electrically-conductive material disposed over the second IC pad, and a diffusion barrier layer that is disposed over the rigid electrically-conductive material; and

wherein, after said electrically connecting, the malleable electrically-conductive material is substantially disposed between the first barrier layer and the diffusion barrier layer and the rigid electrically-conductive material is at least partially enclosed within the malleable electrically-conductive material such that the diffusion barrier layer is configured to prevent interdiffusion of the malleable electrically-conductive material with the rigid electrically-conductive material.

21. The method of claim 20, wherein the second chip further comprises a second barrier layer over the second IC pad, and wherein the rigid electrically-conductive material is located between the malleable electrically-conductive material and one of the first or second barrier layers after said electrically connecting.

22. The method of claim 21, wherein the rigid electrically conductive material and at least one of the first barrier layer or the second barrier layer comprise the same metal, and wherein the second barrier layer is in direct contact with both the second IC pad and the malleable electrically-conductive material after said electrically connecting.

23. The method of claim 20, wherein the diffusion barrier layer is in direct contact with both the rigid electrically-conductive material and the malleable electrically-conductive material after said electrically connecting.

24. The method of claim 23, wherein the first barrier layer is in direct contact with both the first IC pad and the malleable electrically-conductive material.

25. The method of claim 20, wherein said electrically connecting the first electrical contact of the first chip with the second electrical contact of the second chip comprises penetrating the rigid electrically-conductive material into the malleable electrically-conductive material at a temperature below the melting point of the malleable electrically-conductive material.

26. The method of claim 20, wherein the first barrier layer completely covers the first IC pad prior to said electrically connecting.

27. The method of claim 20, wherein the diffusion barrier layer completely covers the second IC pad prior to said electrically connecting.

28. The method of claim 20, wherein the malleable electrically-conductive material is in direct contact with both the first barrier layer and the diffusion barrier layer after said electrically connecting.