Fin spacer protected source and drain regions in FinFETs

• US 9,147,682 B2
• Filed: 10/17/2013
• Issued: 09/29/2015
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Hsu, Ting-Hung, Wang, Chao-Hsiung, Liu, Chi-Wen
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US14/056,649
• Publication Number:
  US 20150108544A1
• Time in Patent Office: 712 Days
• Field of Search: 257/365, 257/E29.264, 257/E29.275, 438/283, 438/157
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions.

Claims

1. An integrated circuit device comprising:

a semiconductor substrate;

insulation regions extending into the semiconductor substrate;

a semiconductor fin protruding above the insulation regions, wherein the insulation regions comprise a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin;

a silicon strip, with opposite edges of the silicon strip contacting sidewalls of the first portion and the second portion of the insulation regions, wherein the semiconductor fin overlaps the silicon strip;

a gate stack on a top surface and sidewalls of the semiconductor fin;

a semiconductor region connected to an end of the semiconductor fin, wherein the semiconductor region comprises;

a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces; and

a second semiconductor region underlying the first semiconductor region, wherein the second semiconductor region has a higher germanium concentration than the first semiconductor region; and

a fin spacer on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions.

2. The integrated circuit device of claim 1 further comprising a gate spacer on a sidewall of the gate stack, wherein the gate spacer is connected to the fin spacer.

3. The integrated circuit device of claim 2, wherein the gate spacer is continuously connected to the fin spacer, with no interface therebetween, and wherein the gate spacer and the fin spacer are formed of a same dielectric material.

4. The integrated circuit device of claim 1, wherein the semiconductor fin comprises:

a top portion; and

a bottom portion, wherein the bottom portion has a first germanium percentage higher than a second germanium percentage of the top portion.

5. The integrated circuit device of claim 4, wherein a width of the bottom portion of the semiconductor fin is smaller than a width of the top portion of the semiconductor fin.

6. The integrated circuit device of claim 1, wherein the fin spacer overlaps the first portion of the insulation regions, with the fin spacer and the insulation regions comprising different dielectric materials.

7. The integrated circuit device of claim 1, wherein the first semiconductor material comprises an epitaxial material, whererin the second semiconductor region comprises a first epitaxial layer underlying a second epitaxial layer.

8. The integrated circuit device of claim 7, wherein the first epitaxial layer has a higher germanium concentration than the second epitaxial layer.

9. The integrated circuit device of claim 7, wherein the fin spacer comprises an edge contacting the sidewall of the second semiconductor region, and wherein a top end of the edge extends further away from the substrate than a top surface of the second epitaxial layer.

10. An integrated circuit device comprising:

a semiconductor substrate;

insulation regions extending into the semiconductor substrate; and

a Fin Field-Effect Transistor (FinFET) comprising;

a first silicon fin and a second silicon fin over the insulation regions and parallel to each other;

a gate stack over a middle portion of the first silicon fin and a middle portion of the second silicon fin;

a first source/drain region and a second source/drain region connected to the first silicon fin and the second silicon fin, respectively, wherein the first source/drain region and the second source/drain region are on a same side of the gate stack;

a fin spacer between the first source/drain region and the second source/drain region, wherein a bottom surface of the fin spacer is in contact with a top surface of the insulation regions;

a germanium-containing region overlapped by the first silicon fin; and

a silicon strip overlapped by the first silicon fin and the germanium-containing region, wherein opposite sidewalls of the silicon strip are in contact with sidewalls of the insulation regions.

11. The integrated circuit device of claim 10, wherein the insulation regions comprise an oxide, and the fin spacer comprises a nitride in physical contact with the oxide.

12. The integrated circuit device of claim 10, wherein the fin spacer comprises a first edge and a second edge contacting the first source/drain region and the second source/drain region, respectively, and wherein thicknesses of edge portions of the fin spacer are greater than a thickness of a center portion of the fin spacer.

13. The integrated circuit device of claim 12, wherein the first source/drain region comprises a second epitaxial layer overlying a first epitaxial layer, and wherein a top end of the first edge of the fin spacer is further away from the substrate than a top surface of the second epitaxial layer of the first source/drain region.

14. The integrated circuit device of claim 10 further comprising a gate spacer on a sidewall of the gate stack, wherein the gate spacer is connected to the fin spacer.

15. The integrated circuit device of claim 14, wherein the gate spacer is continuously connected to the fin spacer, with no interface therebetween, and wherein the gate spacer and the fin spacer are formed of a same dielectric material.

16. The integrated circuit device of claim 10 further comprising:

silicon oxide regions on opposite sides of, and in contact with, the germanium-containing region.

17. An integrated circuit device comprising:

a semiconductor substrate;

insulation regions extending into the semiconductor substrate;

a gate stack over the insulation regions;

a semiconductor region between two portions of the insulation regions, wherein the semiconductor region comprises;

a middle portion covered by the gate stack, wherein the middle portion comprises a first silicon germanium portion and a silicon portion overlapping the first silicon germanium portion; and

an end portion not covered by the gate stack, wherein the end portion is connected to the middle portion, and comprises a second silicon germanium portion and a silicon phosphorous portion overlapping the second silicon germanium portion, wherein the first silicon germanium portion has a germanium percentage higher than a germanium percentage of the second silicon germanium portion; and

silicon oxide regions on opposite sides of the first silicon germanium portion, wherein the silicon oxide regions have portions overlapped by the silicon portion of the middle portion.

18. The integrated circuit device of claim 17, wherein the first silicon germanium portion is coplanar with at least a middle portion of the second silicon germanium portion.

19. The integrated circuit device of claim 17 further comprising a fin spacer over the insulation regions and contacting a sidewall of the second silicon germanium portion.

20. The integrated circuit device of claim 17, wherein the first silicon germanium portion forms a channel of a Fin Field-Effect Transistor (FinFET), and the second silicon germanium portion forms a source/drain region of the FinFET.

21. The integrated circuit device of claim 17, wherein the first silicon germanium portion is narrower than the second silicon germanium portion.