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Fin spacer protected source and drain regions in FinFETs

  • US 9,147,682 B2
  • Filed: 10/17/2013
  • Issued: 09/29/2015
  • Est. Priority Date: 01/14/2013
  • Status: Active Grant
First Claim
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1. An integrated circuit device comprising:

  • a semiconductor substrate;

    insulation regions extending into the semiconductor substrate;

    a semiconductor fin protruding above the insulation regions, wherein the insulation regions comprise a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin;

    a silicon strip, with opposite edges of the silicon strip contacting sidewalls of the first portion and the second portion of the insulation regions, wherein the semiconductor fin overlaps the silicon strip;

    a gate stack on a top surface and sidewalls of the semiconductor fin;

    a semiconductor region connected to an end of the semiconductor fin, wherein the semiconductor region comprises;

    a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces; and

    a second semiconductor region underlying the first semiconductor region, wherein the second semiconductor region has a higher germanium concentration than the first semiconductor region; and

    a fin spacer on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions.

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