Group 13 nitride semiconductor device and method of its manufacture

• US 9,147,732 B2
• Filed: 05/03/2013
• Issued: 09/29/2015
• Est. Priority Date: 05/09/2012
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Donkers, Johannes Theodorus Marinus, Heil, Stephan, Delhougne, Romain, Broekman, Hans
• Primary Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US13/887,065
• Publication Number:
  US 20130299846A1
• Time in Patent Office: 879 Days
• Field of Search: 257/76, 257/15, 257/743, 257/102, 257/103, 438/571, 438/29, 438/46, 438/509, 438/796
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462

Abstract

Disclosed is a semiconductor device comprising a substrate (10); at least one semiconducting layer (12) comprising a nitride of a group 13 element on said substrate; and an ohmic contact (20) on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion (22) on the at least one semiconducting layer and a metal portion (24) adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal. A method of manufacturing such a semiconductor device is also disclosed.

Claims

1. A semiconductor device comprising:

a substrate;

at least one semiconducting layer comprising a nitride of a group 13 element on said substrate; and

an ohmic contact on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion on the at least one semiconducting layer and a metal portion adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal, wherein the ohmic contact does not contain gold, wherein the metal portion comprises a titanium layer, a layer of the further metal over the titanium layer, and a capping layer made of a material containing titanium for protecting the layer of the further metal, wherein the silicon-comprising portion comprises a first silicon-comprising portion and a second silicon-comprising portion laterally separated from the first silicon-comprising portion, wherein a part of the metal portion extends between the first silicon-comprising portion and the second silicon-comprising portion, and wherein the metal portion completely envelopes the first silicon-comprising portion and the second silicon-comprising portion.

2. The semiconductor device of claim 1, wherein the silicon source of the silicon-comprising portion is selected from silicon, silicon oxide and silicon nitride.

3. The semiconductor device of claim 1, wherein the metal portion comprises:

the titanium layer on the at least one semiconducting layer and extending over the silicon-comprising portion; and

the layer of the further metal over the titanium layer; and

/or

an alloy layer of said titanium and the further metal.

4. The semiconductor device of claim 1, wherein the first silicon-comprising portion and the second silicon-comprising portion are spacers or stripes.

5. The semiconductor device of claim 1, wherein the nitride of a group 13 element is selected from aluminum nitride, gallium nitride and indium nitride.

6. The semiconductor device of claim 4, wherein the at least one semiconducting layer on said substrate comprises a gallium nitride layer and an aluminum gallium nitride barrier layer in between said gallium nitride layer and the ohmic contact.

7. The semiconductor device of claim 1, wherein the further metal is aluminum.

8. An integrated circuit comprising a semiconductor device of claim 1.

9. The semiconductor device of claim 1, wherein the capping layer is made of TiW or TiN.

10. The semiconductor device of claim 1, wherein the first and second silicon-comprising portions are in direct contact with the at least one semiconducting layer, and wherein the first and second silicon-comprising portions are completely covered by the titanium layer.

11. A method of manufacturing a semiconductor device, comprising:

providing a substrate having thereon at least one semiconducting layer comprising a nitride of a group 13 element; and

forming an ohmic contact on the at least one semiconducting layer by;

forming a silicon-comprising layer on the at least one semiconducting layer;

patterning said silicon-comprising layer to form a silicon-comprising portion;

forming a metal portion metal portion adjacent to and extending over said silicon-comprising portion by;

depositing a metal portion comprising titanium and a further metal on the resultant structure said metal portion not containing gold, wherein the metal portion comprises a titanium layer, a layer of the further metal over the titanium layer, and a capping layer made of a material containing titanium for protecting the layer of the further metal, wherein the silicon-comprising portion comprises a first silicon-comprising portion and a second silicon-comprising portion laterally separated from the first silicon-comprising portion, wherein a part of the metal portion extends between the first silicon-comprising portion and the second silicon-comprising portion, and wherein the metal portion completely envelopes the first silicon-comprising portion and the second silicon-comprising portion; and

patterning the metal portion and the patterned silicon-comprising layer using at least one etch recipe; and

annealing the resultant structure to react the metal portion with silicon from the silicon-comprising layer.

12. The method of claim 11, wherein the step of depositing a metal portion comprises depositing a titanium layer on the resultant structure and depositing a further metal layer such as an aluminum layer on the titanium layer.

13. The method of claim 11, wherein the metal portion is deposited by evaporation or physical vapor deposition.

14. The method of claim 11, wherein said patterning step comprises:

patterning the metal portion using the silicon-comprising portion as an etch stop; and

further patterning the silicon-comprising portion using the at least one semiconducting layer as an etch stop.

15. The method of claim 11, wherein said annealing step is performed in a range of 600-900°

C.