Flip-flop circuit with resistive poly routing

• US 9,148,149 B2
• Filed: 02/07/2014
• Issued: 09/29/2015
• Est. Priority Date: 03/25/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cheng, Zhihong, Wang, Peidong
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US14/176,025
• Publication Number:
  US 20140285236A1
• Time in Patent Office: 599 Days
• Field of Search: 326 56- 58
• US Class Current: 1/1
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.

Claims

1. A latch circuit, comprising:

a tri-state gate having an input, an output, and receiving complementary control signals;

a reverse tri-state gate having an input, an output, and sharing the complementary control signals with the tri-state gate, wherein the reverse tri-state gate is configured to lock an output of the tri-state gate when the tri-state gate is shut-off;

a first undoped polysilicon strip for generating one of the complementary control signals; and

a second undoped polysilicon strip coupled between the output of the tri-state gate and the output of the reverse tri-state gate.

2. The latch circuit of claim 1, wherein each of the first and second undoped polysilicon strips has a resistance more than 200 ohms.

3. The latch circuit of claim 1, wherein the tri-state gate comprises:

upper and lower PMOS transistors in cascode arrangement with upper and lower NMOS transistors,

wherein the tri-state gate receives the complementary control signals at the gate electrodes of the lower PMOS transistor and the upper NMOS transistor, receives input signal at the gate electrodes of the upper PMOS transistor and the lower NMOS transistor, and provides the output at the drain electrodes of the lower PMOS transistor and the upper NMOS transistor.

4. The latch circuit of claim 1, wherein the tri-state gate comprises:

a PMOS transistor; and

a NMOS transistor, wherein the source and drain of the NMOS transistor are coupled to the drain and source of the PMOS transistor, respectively, and

wherein the tri-state gate receives the complementary control signals at the gate electrodes of the PMOS transistor and the NMOS transistor, receives the input signal at the source electrode of the PMOS transistor and the drain electrode of the NMOS transistor, and provides the output at the drain electrode of the PMOS transistor and the source electrode of the NMOS transistor.

5. A latch circuit, comprising:

a tri-state gate having an input, an output, and receiving complementary control signals;

a reverse tri-state gate having an input connected to an output of the tri-state gate, an output, and sharing the complementary control signals with the tri-state gate;

an inverter connected between the output of the tri-state gate and the input of the reverse tri-state gate, wherein the reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off;

a first undoped polysilicon strip that receives a clock signal and generates one of the complementary control signals; and

a second undoped polysilicon strip coupled between the output of the tri-state gate and the output of the reverse tri-state gate.

6. A flip-flop circuit, comprising:

a first latch circuit having;

a first tri-state gate having an input, an output and receiving complementary control signals; and

a first reverse tri-state gate having an input, an output and sharing the complementary control signals with the first tri-state gate, wherein the first reverse tri-state gate is configured to lock an output of the first tri-state gate when the first tri-state gate is shut-off; and

a second latch circuit connected in series with the first latch circuit, the second latch circuit having;

a second tri-state gate that shares the complementary control signals with the first tri-state gate, wherein the second tri-state gate is configured to be in an on/off state opposite to the first tri-state gate; and

a second reverse tri-state gate that shares the same complementary control signals with the first tri-state gate, wherein the second reverse tri-state gate is configured to lock an output of the second tri-state gate when the second tri-state gate is shut-off,

wherein the complementary control signals comprise a first undoped polysilicon strip, and the output of the first reverse tri-state gate is coupled to the output of the first tri-state gate via a second undoped polysilicon strip, and the output of the second reverse tri-state gate is coupled to the output of the second tri-state gate via a third undoped polysilicon strip.

7. The flip flop circuit of claim 6, wherein each of the first, second and third undoped polysilicon strips has a resistance more than 200 ohms.

8. The flip flop circuit of claim 6, wherein at least one of the first and second tri-state gates comprises:

upper and lower PMOS transistors in cascode arrangement with upper and lower NMOS transistors;

wherein the at least one of the first and second tri-state gates receives the complementary control signals at the gate electrodes of the lower PMOS transistor and the upper NMOS transistor, receives the input signal at the gate electrodes of the upper PMOS transistor and the lower NMOS transistor, and provides the output at the drain electrodes of the lower PMOS transistor and the upper NMOS transistor.

9. The flip flop circuit of claim 6, wherein at least one of the first and second reverse tri-state gates comprises:

a PMOS transistor; and

a NMOS transistor, wherein the source and drain of the NMOS transistor are coupled to the drain and source of the PMOS transistor, respectively, and

wherein the at least one of the first and second reverse tri-state gates receives the complementary control signals at the gate electrodes of the PMOS transistor and the NMOS transistor, receives the input signal at the source electrode of the PMOS transistor and the drain electrode of the NMOS transistor, and provides the output at the drain electrode of the PMOS transistor and the source electrode of the NMOS transistor.