Methods and arrangements for error correction in decoding data from an electromagnetic radiator

• US 9,148,250 B2
• Filed: 06/30/2012
• Issued: 09/29/2015
• Est. Priority Date: 06/30/2012
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Roberts, Richard D., Gopalakrishnan, Praveen, Walma, Mathys C., Yang, Lei T.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/539,354
• Publication Number:
  US 20140006907A1
• Time in Patent Office: 1,186 Days
• Field of Search: 714/776, 714/745, 714/725, 714/705, 714/704, 714/731, 714/48, 714/26
• US Class Current: 1/1
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end

Abstract

Embodiments may communicate via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode lighting via receivers that can determine data from light received from the radiator. Some embodiments decode data of a packet transmitted from modulated lighting by means of a device with a low sampling frequency such as a relatively inexpensive camera. Many embodiments determine locations of start frame delimiters in packets. Several embodiments implement repeat decoding on packets of the same data to reduce packet error rates. Some embodiments are intended for indoor navigation via photogrammetry using self-identifying light anchors. In many embodiments, the data signal may be communicated via the light source at frequencies causing flicker that is not perceivable to the human eye.

Claims

1. A method for error correction in decoding data comprising:

receiving, by an apparatus, values determined from frames, the values indicative of light emanated from a light source, wherein the frames comprise a packet of data;

processing, by the apparatus, the values to determine chips, wherein processing the values comprises selecting chips indicative of the values, wherein the chips are indicative of on and off states of the light source in the respective frames;

processing, by the apparatus, the chips to determine a location of a start frame delimiter within the chips; and

processing, by the apparatus, the chips, based upon the location of the start frame delimiter within the chips, to determine bits of the packet of data.

2. The method of claim 1, further comprising capturing the frames as video at a sampling frequency.

3. The method of claim 1, wherein receiving values comprises receiving values determined from frames of more than one transmissions of the packet of data and wherein processing the chips to determine bits comprises processing the chips of the more than one transmissions of the packet of data with repeat decoding.

4. The method of claim 1, wherein processing the values to determine chips comprises forming the values into a vector representative of the packet and determining a threshold between the minimum and maximum of the values.

5. The method of claim 4, wherein processing the values to determine chips comprises determining the chips from the values based upon the threshold.

6. The method of claim 4, wherein processing the values comprises determining a variance and discarding a packet with the least variance.

7. The method of claim 1, wherein processing the chips to determine the location of the start frame delimiter comprises identifying a pattern indicative of the start frame delimiter.

8. The method of claim 1, wherein processing the chips to determine the location of the start frame delimiter comprises calculating magnitudes of Fourier Transform bins for two or more chips via Fourier transform processing, or determining commensurate patterns in the time domain via time domain processing.

9. The method of claim 1, wherein processing the chips to determine the bits comprises calculating magnitudes of Fourier Transform bins for two or more chips representative of a single bit via Fourier transform processing, or determining commensurate patterns in the time domain via time domain processing.

10. The method of claim 1, wherein processing the chips to determine the bits comprises assigning a first bit position to a first bit derived from chips immediately following the start frame delimiter in a vector of the chips that represent the packet.

11. An apparatus for error correction in decoding data comprising:

sample logic to receive values determined from frames, the values indicative of light emanated from a light source, wherein the frames comprise a packet of data; and

to process the values to determine chips by selecting chips indicative of the values, wherein the chips are indicative of on and off states of the light source in the respective frames; and

a data associator coupled with frequency logic to process the chips to detect a location of a start frame delimiter within the chips; and

to process the chips, based upon the location of the start frame delimiter within the chips, to determine bits of the packet of data.

12. The apparatus of claim 11, wherein the sample logic comprises vector logic to determine a vector of values indicative of the packet.

13. The apparatus of claim 11, wherein the sample logic comprises threshold logic to determine a threshold between a minimum and maximum of the values.

14. The apparatus of claim 13, wherein the sample logic comprises sign logic to determine a chip associated with a value based upon a difference between the value and the threshold.

15. The apparatus of claim 14, wherein the sample logic comprises variance logic to determine a variance associated with the chip based upon the difference between the value and the threshold.

16. The apparatus of claim 11, wherein the sample logic comprises linear logic to determine a linear vector of values indicative of the packet based upon the location of the start frame delimiter.

17. The apparatus of claim 11, wherein the frequency logic comprises Fourier transform logic to determine magnitudes of more than one frequency bins.

18. The apparatus of claim 11, wherein the data associator comprises start frame delimiter logic to detect apparent locations of the start frame delimiter based upon magnitudes of more than one of the chips at more than one frequencies and to determine the location of the start frame delimiter.

19. The apparatus of claim 11, wherein the data associator comprises repeat decoding logic to determine an odd number of determinations of bits of the packet and to determine values of bits of the packet based upon the odd number of determinations of bits of the packet.

20. The apparatus of claim 11, wherein the data associator comprises repeat decoding logic to determine an odd number of determinations of bits of the packet by eliminating a determination of bits of the packet based upon a variance associated with the packet.

21. A system for error correction in decoding data comprising:

a light detector to detect light in frames from light source at a sampling frequency to produce values associated with the light for the respective frames;

sample logic to receive the values determined from the frames, the values indicative of light emanated from a light source, wherein the frames comprise a packet of data; and

to process the values to determine chips by selecting chips indicative of the values, wherein the chips are indicative of on and off states of the light source in the respective frames; and

a data associator coupled with frequency logic to process the chips to detect a location of a start frame delimiter within the chips; and

to process the chips, based upon the location of the start frame delimiter within the chips, to determine bits of the packet of data.

22. The system of claim 21, wherein the light detector comprises a camera to capture frames of pixels.

23. The system of claim 21, wherein the sample logic comprises variance logic to determine a variance associated with the chip based upon the difference between the value and the threshold.

24. The system of claim 21, wherein the frequency logic comprises logic to perform a Fourier transform, or time domain processing to identify commensurate patterns in the time domain, with the samples to determine at least the magnitudes of the waveform at the apparent frequencies.

25. The system of claim 21, wherein the data associator comprises start frame delimiter logic to detect apparent locations of the start frame delimiter based upon magnitudes of more than one of the chips at more than one frequencies and to determine the location of the start frame.

26. The system of claim 21, wherein the data associator comprises repeat decoding logic to determine an odd number of determinations of bits of the packet and to determine values of bits of the packet based upon the odd number of determinations of bits of the packet.

27. The system of claim 21, wherein the data associator comprises repeat decoding logic to determine an odd number of determinations of bits of the packet by eliminating a determination of bits of the packet based upon a variance associated with the packet.

28. A program product for error correction in decoding data comprising:

a storage medium comprising instructions to be executed by a processor-based device, wherein the instructions, when executed by the processor-based device, perform operations, the operations comprising;

receiving values determined from frames, the values indicative of light emanated from a light source, wherein the frames comprise a packet of data;

processing the values to determine chips, wherein processing the values comprises selecting chips indicative of the values, wherein the chips are indicative of on and off states of the light source in the respective frames;

processing the chips to detect a location of a start frame delimiter within the chips; and

processing the chips, based upon the location of the start frame delimiter within the chips, to determine bits of the packet of data.

29. The program product of claim 28, wherein the operations further comprise capturing the frames as video at a sampling frequency.

30. The program product of claim 28, wherein receiving values comprises receiving values determined from frames of more than one transmissions of the packet of data and wherein processing the chips to determine bits comprises processing the chips of the more than one transmissions of the packet of data with repeat decoding.