High-speed signaling systems with adaptable pre-emphasis and equalization
First Claim
Patent Images
1. A system comprising:
- a transmitter having circuitry to equalize data to be transmitted over a signaling path, the circuitry including a post-cursor tap, a main tap, and a pre-cursor tap; and
a receiver to receive the data, the receiver havinga linear equalizer to equalize the data received from the signaling path, anda decision-feedback equalizer with one or more taps to equalize an output of the linear equalizer;
where, in a first power mode, the circuitry enables the pre-cursor tap to equalize the data to be transmitted to the receiver only for pre-tap interference, and disables the post-cursor tap; and
where, in a second power mode, the post-cursor tap is enabled, and the linear equalized is disabled.
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Abstract
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
84 Citations
25 Claims
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1. A system comprising:
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a transmitter having circuitry to equalize data to be transmitted over a signaling path, the circuitry including a post-cursor tap, a main tap, and a pre-cursor tap; and a receiver to receive the data, the receiver having a linear equalizer to equalize the data received from the signaling path, and a decision-feedback equalizer with one or more taps to equalize an output of the linear equalizer; where, in a first power mode, the circuitry enables the pre-cursor tap to equalize the data to be transmitted to the receiver only for pre-tap interference, and disables the post-cursor tap; and where, in a second power mode, the post-cursor tap is enabled, and the linear equalized is disabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system comprising:
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a transmitter having circuitry to equalize data to be transmitted over a signaling path, the circuitry including a post-cursor tap, a main tap, and a pre-cursor tap, the circuitry to equalize the data only for precursor interference; and a receiver to receive the data, the receiver having a linear equalizer to equalize the data received from the signaling path, and a decision-feedback equalizer (DFE) with one or more taps to equalize an output of the linear equalizer only for post cursor interference; where, in a first power mode, the decision-feedback equalizer is to equalize the output of the linear equalizer for symbols of latency greater than a predetermined latency, and where the circuitry is to equalize the data for symbol latency not overlapping equalization provided by the decision-feedback equalizer; and where, in a second power mode, the linear equalizer and the one or more taps of the DFE are disabled. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method comprising:
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in a first power mode, using circuitry on a first integrated circuit to equalize an input data signal only for precursor interference and transmit an equalized data signal to a second integrated circuit, the circuitry including a post-cursor tap, a main tap, and a pre-cursor tap; using a linear equalizer on the second integrated circuit to further equalize the equalized data signal to provide a first receiver-equalized signal; and using a decision-feedback equalizer (DFE) on the second integrated circuit to further equalize the first receiver-equalized signal only for post cursor interference to provide a second receiver-equalized signal; where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal for symbol latency exceeding a first latency relative to a current symbol, and where using the circuitry on the first integrated circuit includes equalizing the input data signal for symbol latency not exceeding the first latency relative to the current symbol; and in a second power mode, disabling the linear equalizer and the DFE, and using the circuitry to equalize for post-cursor intersymbol interference. - View Dependent Claims (24)
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25. A method comprising:
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in a first power mode, using circuitry on a first integrated circuit to equalize an input data signal only for precursor interference and transmit an equalized data signal to a second integrated circuit, the circuitry including a post-cursor tap, a main tap, and a pre-cursor tap; using a linear equalizer on the second integrated circuit to further equalize the equalized data signal to provide a first receiver-equalized signal; and using a decision-feedback equalizer (DFE) on the second integrated circuit to further equalize the first receiver-equalized signal only for post cursor interference to provide a second receiver-equalized signal; where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal for symbol latency exceeding a first latency relative to a current symbol, and where using the circuitry on the first integrated circuit includes equalizing the input data signal for symbol latency not overlapping the decision-feedback equalizer; and in a second power mode, disabling the linear equalizer and the DFE, and using the circuitry to equalize for post-cursor intersymbol interference.
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Specification