Framework for runtime power monitoring and management

• US 9,152,218 B2
• Filed: 03/25/2011
• Issued: 10/06/2015
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Muralidhar, Rajeev D., Seshadri, Harinarayanan, Mahalingam, Nithish, Kadam, Rushikesh S., Rudramuni, Vishwesh M., Thomas, Sujith
• Primary Examiner(s): Lee, Tammy
• Application Number:
  US13/071,877
• Publication Number:
  US 20120167109A1
• Time in Patent Office: 1,656 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.

Claims

1. An apparatus comprising:

a processor, and

logic to,

monitor a runtime power consumption of two or more of a plurality of hardware components in a platform to obtain a plurality of runtime power determinations,

expose one or more of the plurality of runtime power determinations to an operating system associated with the platform, and

expose a table stored in memory to the operating system, wherein the table is to include a voltage rail number to identify a voltage rail corresponding to one or more of the plurality of hardware components,

wherein, for one or more of the plurality of runtime power determinations, the logic is to,

measure power drawn from the voltage rail,

provide the measured power drawn to an analog to digital converter to conduct an analog to digital conversion of the measured power drawn,

write the measured power drawn to a shared result register that is to be independent of the plurality of hardware components and that is to be coupled to the analog to digital converter to generate a result register entry, wherein the entry is to correspond to a hardware component coupled to the voltage rail, and

accumulate at an accumulator to be located between the analog to digital converter and the shared result register the measured power drawn based on an accumulation value of a control register, wherein the accumulation value is to define a time period to accumulate the measured power drawn.

2. The apparatus of claim 1, wherein the logic is to control the voltage rail based on a throttle value of the control register.

3. The apparatus of claim 1, wherein the logic is to,

identify a clock domain in the platform for two or more of the plurality of hardware components to obtain a plurality of clock determinations, and

expose one or more of the plurality of clock determinations to the operating system.

4. The apparatus of claim 1, wherein the table is to include an array of subsystem-to-voltage rail mappings using the voltage rail number, and the logic is to parse through the array to identify the voltage rail.

5. A non-transitory computer readable storage medium comprising a set of stored instructions which, if executed by a processor, cause a computer to:

identify a plurality of runtime power determinations, wherein two or more of the runtime power determinations are to correspond to hardware components of a platform including a subsystem number, and wherein a voltage rail number corresponding to the subsystem number is to be used to identify a voltage rail corresponding to the hardware components to identify the plurality of runtime power determinations;

assign relative priorities to one or more processes based on one or more of the plurality of runtime power determinations; and

schedule the one or more processes to utilize the hardware components of the platform based on the relative priorities independently of a throttling activity,

wherein for one or more of the plurality of runtime power determinations, logic is to;

measure power drawn from the voltage rail;

conduct an analog to digital conversion of the measured power drawn;

write the measured power drawn to a shared result register that is to be independent of the hardware components to generate a result register entry, wherein the entry is to correspond to a hardware component coupled to the voltage rail; and

accumulate the measured power drawn based on an accumulation value of a control register, wherein the accumulation value is to define a time period to accumulate the measured power drawn.

6. The medium of claim 5, wherein the instructions, if executed, further cause a computer to read a table from a memory of the platform, wherein the table is to include the voltage rail number to identify the voltage rail corresponding to one or more hardware components of the platform.

7. The medium of claim 6, wherein for one or more of the plurality of runtime power determinations, if executed, the instructions cause a computer to read the measured power drawn from the result register entry of the shared result register based on the table.

8. The medium of claim 7, wherein the measured power drawn is to be read via at least one of an application programming interface and an inter-process communication.

9. The medium of claim 5, wherein the instructions, if executed, further cause a computer to write a throttle value to a control register based on the plurality of runtime determinations.

10. A computing system comprising:

a plurality of hardware components including a processor,

logic to,

monitor a runtime power consumption of two or more of the plurality of hardware components to obtain a plurality of runtime power determinations, and

expose one or more of the plurality of runtime power determinations to an operating system associated with the computing system, and

a non-transitory computer readable storage medium including a set of stored operating system instructions which, if executed by the processor, cause the computing system to,

identify the plurality of runtime determinations, wherein a voltage rail number is to be used to identify a voltage rail corresponding to the plurality of hardware components to identify the plurality of runtime power determinations,

assign relative priorities to one or more processes based on the plurality of runtime power determinations, and

schedule the one or more processes to utilize the hardware components of the platform based on the relative priorities independently of a throttling activity,

wherein for one or more of the plurality of runtime power determinations, the logic is to,

measure power drawn from the voltage rail,

conduct an analog to digital conversion of the measured power drawn,

write the measured power drawn to a shared result register that is to be independent of the plurality of hardware components to generate a result register entry, wherein the entry is to correspond to a hardware component coupled to the voltage rail, and

accumulate the measured power drawn based on an accumulation value of a control register, wherein the accumulation value is to define a time period to accumulate the measured power drawn.

11. The computing system of claim 10, wherein the logic is to control the voltage rail based on a throttle value of the control register.

12. The computing system of claim 10, wherein the logic is to expose a table to the operating system, and the table is to include the voltage rail number to identify the voltage rail corresponding to one or more of the plurality of hardware components.

13. The computing system of claim 10, wherein the logic is to,

identify a clock domain in the computing system for two or more of the plurality of hardware components to obtain a plurality of clock determinations, and

expose one or more of the plurality of clock determinations to the operating system.

14. The computing system of claim 10, wherein the instructions, if executed, further cause the computing system to read a table from a memory of the computing system, wherein the table is to include the voltage rail number to identify the voltage rail corresponding to one or more of the hardware components of the computing system.

15. The computing system of claim 14, wherein for one or more of the plurality of runtime power determinations, if executed, the instructions cause the computing system to read the measured power drawn from the register result entry of the shared result register based on the table.

16. The computing system of claim 15, wherein the measured power drawn is to be read via at least one of an application programming interface and an inter-process communication.

17. The computing system of claim 10, wherein the instructions, if executed, further cause the computing system to write a throttle value to a control register based on the plurality of runtime determinations.

18. A method comprising:

monitoring a runtime power consumption of two or more of a plurality of hardware components in a platform to obtain a plurality of runtime power determinations;

exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform; and

exposing a table stored in memory to the operating system, wherein the table includes a voltage rail number to identify a voltage rail corresponding to one or more of the plurality of hardware components,

wherein for one or more of the plurality of runtime power determinations, monitoring the runtime power consumption includes;

measuring power drawn from the voltage rail;

conducting an analog to digital conversion of the measured power drawn;

writing the measured power drawn to a shared result register that is independent of the plurality of hardware components to generate a result register entry, wherein the entry corresponds to a hardware component coupled to the voltage rail; and

accumulating the measured power drawn based on an accumulation value of a control register, wherein the accumulation value defines a time period to accumulate the measured power drawn.

19. The method of claim 18, further including controlling the voltage rail based on a throttle value of the control register.

20. The method of claim 18, further including:

identifying a clock domain in the platform for two or more of the plurality of hardware components to obtain a plurality of clock determinations; and

exposing one or more of the plurality of clock determinations to the operating system.

21. The method of claim 18, further including:

mapping the plurality of runtime determinations to one or more processes;

assigning relative priorities to the one or more processes based on the plurality of runtime power determinations;

scheduling the one or more processes based on the relative priorities; and

writing a throttle value to a control register based on the plurality of runtime determinations.

22. The method of claim 21, further including:

reading the table from a memory of the platform; and

reading, for one or more of the plurality of runtime power determinations, the measured power drawn from the register result entry of the shared result register based on the table.

23. The method of claim 22, wherein the measured power drawn is to be read via at least one of an application programming interface and an inter-process communication.

24. The method of claim 18, further including parsing through an array of subsystem-to-voltage rail mappings from the table to identify the voltage rail using the voltage rail number.