Programmable interface-based validation and debug

• US 9,152,520 B2
• Filed: 09/26/2013
• Issued: 10/06/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gahoi, Anshul, Santhanagopal, Raghavendra, Babu, Pradeep Kumar
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/038,743
• Publication Number:
  US 20150089289A1
• Time in Patent Office: 740 Days
• Field of Search: 716/136, 716/106, 716/117, 716/121, 716/128, 714/30, 714/33, 714/733, 324/527, 324/750.15, 324/750.3, 702/118, 702/58
• US Class Current: 1/1
• CPC Class Codes: G01R 13/28 Circuits for simultaneous or sequential presentation of more than one variable
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs

Abstract

A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.

Claims

1. A test fixture, comprising:

a test connector that is arranged to communicatively couple a design under test to the test fixture, said test connector including a shared test bus coupled to a first set of selected pins; and

a programmable logic interface that is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, wherein the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus;

a multiplexer that is arranged to selectively couple one of the first test control bus and a second test control bus to the shared test bus, wherein the second test control bus is arranged to apply test vectors from a second set of test vectors.

2. The test fixture of claim 1, wherein the second set of test vectors is supplied by a debugger that is operable by a human to control execution of the first set of test vectors.

3. The test fixture of claim 2, comprising an arbiter that is arranged to transfer mastership of the shared test bus between the debugger and downloadable test bench.

4. The test fixture of claim 2, wherein the first set of test vectors is arranged to validate a performance of the design under test coupled to the test connector.

5. The test fixture of claim 3, wherein:

the arbiter transfers mastership of the shared test bus dependent upon a command received from the programmable logic interface.

6. The test fixture of claim 3, wherein:

the arbiter transfers mastership of the shared test bus dependent upon contents of the first test control bus.

7. The test fixture of claim 3, wherein:

the arbiter transfers mastership of the shared test bus dependent upon contents of the second test control bus.

8. The test fixture of claim 3, wherein:

the arbiter transfers mastership of the shared test bus dependent upon an output of design under test.

9. The test fixture of claim 1, comprising an addressable memory in which the first set of test vectors is stored.

10. The test fixture of claim 9, wherein the programmable logic interface includes a field-programmable gate array (FPGA) that is programmed to include a program counter that is arranged to generate an address by which test vectors from the first set of test vectors are retrieved.

11. The test fixture of claim 10, wherein the value of the program counter is changed in response to a value of retrieved test vectors from the first set of test vectors.

12. The test fixture of claim 11, wherein a first portion of the first set of retrieved test vectors from the first set of test vectors is applied to the first set of selected pins of the test connector, and wherein a second portion of the first set of retrieved test vectors for the first set of test vectors is applied to a third test bus that is coupled to a second set of selected pins of the test connector, wherein the second set of selected pins of the test connector includes selected pins that are different from the selected pins in the first set of selected pins.