Data management with modular erase in a data storage system

• US 9,152,555 B2
• Filed: 11/15/2013
• Issued: 10/06/2015
• Est. Priority Date: 11/15/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Higgins, James M., Ellis, Robert W., Dancho, Mark, Fitzpatrick, James
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US14/082,031
• Publication Number:
  US 20150143068A1
• Time in Patent Office: 690 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A system and method of data management with modular erase in a data storage system with a memory array having an erase block and a target block with the target block in a logical unit separate from the erase block including: performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block; updating a command status for the erase block; enabling an intervening command on the target block based on the command status indicating an incomplete erase status with the intervening command updating the command status; performing an erase optimization based on the command status; performing an additional erase operation based on the erase optimization; and updating the command status to an erase complete status based on the additional erase operation.

Claims

1. A method of data management with modular erase in a data storage system with a non-volatile memory array having an erase block and a target block with the target block in a logical unit separate from the erase block, comprising:

performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block;

updating a command status for the erase block;

enabling an intervening command on the target block, based on the command status indicating an incomplete erase status, with the intervening command updating the command status;

performing an erase optimization based on the command status;

performing an additional erase operation based on the erase optimization; and

updating the command status to an erase complete status based on the additional erase operation.

2. The method as claimed in claim 1 further comprising:

calculating a memory age of the erase block based on age metrics; and

performing the erase optimization based on the memory age.

3. The method as claimed in claim 1 wherein:

performing the erase optimization includes calculating erase operation values for the operation matrix; and

performing the additional erase operation with the erase operation values.

4. The method as claimed in claim 1 further comprising:

calculating a dwell time for the erase block; and

implementing a dwell delay for the dwell time before the additional erase operation to increase endurance.

5. The method as claimed in claim 1 wherein performing the intervening command includes implementing a total execution time for the erase operation that is less than a maximum execution time.

6. The method as claimed in claim 1 wherein enabling the intervening command includes performing more than one of the intervening command between the erase operation and another of the erase operation.

7. A data storage system comprising:

a controller coupled to a non-volatile memory array having an erase block and a target block, the target block in a logical unit separate from the erase block;

a configuration module for configuring an erase operation to be performed on the erase block;

a partial erase module coupled to the configuration module for performing the erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block, the erase operation updating a command status for the erase block, and for performing an additional erase operation based on an erase optimization;

an intervening command module coupled to the partial erase module for performing an intervening command on the target block based on the command status indicating an incomplete erase status, with the intervening command updating the command status;

an optimization module coupled to the intervening command module for performing the erase optimization based on the command status; and

an update module coupled to the optimization module for updating the command status to an erase complete status based on the additional erase operation;

wherein the configuration module, the partial erase module, the intervening command module, the optimization module and the update module include executable instructions executed by a control unit of the controller.

8. The system as claimed in claim 7 further comprising:

a check status module coupled to the partial erase module for calculating a memory age of the erase block based on age metrics; and

wherein;

the optimization module is for performing the erase optimization based on the memory age.

9. The system as claimed in claim 7 wherein:

the optimization module is for calculating erase operation values for the operation matrix; and

the partial erase module is for performing the additional erase operation with the erase operation values.

10. The system as claimed in claim 7 wherein:

the optimization module includes a dwell time module for calculating a dwell time for the erase block; and

the partial erase module is for implementing a dwell delay for the dwell time before the additional erase operation to increase endurance.

11. The system as claimed in claim 7 wherein the optimization module includes a total time module for implementing a total execution time less than a maximum execution time.

12. The system as claimed in claim 7 wherein the intervening command module is for performing more than one of the intervening command between the erase operation and another of the erase operation.

13. The system as claimed in claim 7 further comprising:

a check status module coupled to the partial erase module for calculating a memory age of the erase block; and

wherein;

the optimization module is for calculating erase operation values for the operation matrix, the erase operation values having an erase voltage and an erase pulse width, and for setting the erase voltage based on the memory age, the erase voltage having a higher value for larger values of the memory age; and

the partial erase module is for performing the additional erase operation with the erase voltage and the erase pulse width for partially erasing the erase block.

14. A data storage system comprising:

a controller coupled to a non-volatile memory array having an erase block and a target block, the target block in a logical unit separate from the erase block;

the controller including;

a control unit coupled to the non-volatile memory array for performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block, the erase operation updating a command status for the erase block, for performing an intervening command on the target block, based on the command status indicating an incomplete erase status, with the intervening command updating the command status, and for performing an additional erase operation based on an erase optimization;

a memory interface having circuitry for communicating with the non-volatile memory array; and

a database coupled to the control unit to store read threshold information; and

array logic for coupling the non-volatile memory array to the memory interface of the controller;

wherein the control unit, the memory interface, and the array logic comprise hardware logic.

15. The system as claimed in claim 14 wherein:

the control unit is for calculating a memory age of the erase block based on age metrics; and

the array logic is for performing the erase optimization based on the memory age.

16. The system as claimed in claim 14 wherein:

the database is for calculating erase operation values for the operation matrix; and

the control unit is for performing the additional erase operation with the erase operation values.

17. The system as claimed in claim 14 wherein the control unit is for calculating a dwell time for the erase block and for implementing a dwell delay for the dwell time before the additional erase operation to increase endurance.

18. The system as claimed in claim 14 wherein the array logic is for implementing a total execution time less than a maximum execution time.

19. The system as claimed in claim 14 wherein the memory interface is for performing more than one of the intervening command between the erase operation and another of the erase operation.

20. The system as claimed in claim 14 wherein the control unit is for calculating a memory age of the erase block, for calculating erase operation values for the operation matrix, the erase operation values having an erase voltage and an erase pulse width, for setting the erase voltage based on the memory age with the erase voltage having a higher value for larger values of the memory age, and for performing the additional erase operation with the erase voltage and the erase pulse width configured for partially erasing the erase block.